run_vera

FEATURES &#8226 16 bit PIPE Spec PCI Express Testbench &#8226 Link training &#8226 Initial Flo

#!/bin/csh -f

\rm -rf simv csrc simv.daidir comp.log sim.log

 vcs -ntb ti_phy_top.test_top.v ti_phy_top.v ti_phy_top.vr \
    -P /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/debussy.tab \
       /usr/local/PLI/NS-VCS/LINUX/LINUX_PLI/pli.a \
    -Mupdate -l vcs_compile.log +vcs+lic+wait +define+SYNOPSYS_NTB -l comp.log $*

 ./simv -l sim.log $*