aes128_spartan_delay
来自「Consecutive AES core Description of p」· 代码 · 共 165 行
TXT
165 行
Clock Frequency Report Clock : Frequency ------------------------------------ clk : 101.3 MHz Critical Path ReportCritical path #1, (path slack = 0.1):NAME GATE ARRIVAL LOAD--------------------------------------------------------------------------------------------clock information not specifieddelay thru clock network 0.00 (ideal)reg_s3_buf(1)(3)/Q FDC 0.00 0.53 up 1.50ix36548_ix910/O LUT4 0.72 1.25 up 0.50ix36548_ix913/O MUXF5 0.38 1.63 up 0.50ix36548_ix919/O MUXF6 0.24 1.86 up 0.50ix36548_ix933/O MUXF7 0.24 2.10 up 0.50ix36548_ix963/O MUXF8 0.24 2.34 up 0.80r_02(1)(6)/O LUT3 0.72 3.06 up 1.00nx14310/O LUT4 0.72 3.78 up 0.60modgen_xor_11683_nx2/O LUT4 0.72 4.50 up 0.50a(0)_dup_37693/O LUT4 0.72 5.22 up 1.00modgen_xor_11685_nx10/O LUT4 0.72 5.94 up 0.50modgen_xor_11685_ix13/LO LUT4_L 0.72 6.66 up 0.50nx40772/O LUT3 0.72 7.37 up 0.50next_round_data_2(0)(4)/O LUT4 0.72 8.09 up 0.60nx27520/O LUT4 0.72 8.81 up 0.60reg_s2_buf(0)(4)/D FDC 0.00 8.81 up 0.00data arrival time 8.81data required time (default specified - setup time) 8.94--------------------------------------------------------------------------------------------data required time 8.94data arrival time 8.81 ----------slack 0.13--------------------------------------------------------------------------------------------Critical path #2, (path slack = 0.1):NAME GATE ARRIVAL LOAD--------------------------------------------------------------------------------------------clock information not specifieddelay thru clock network 0.00 (ideal)reg_s3_buf(1)(2)/Q FDC 0.00 0.53 up 1.50ix36548_ix910/O LUT4 0.72 1.25 up 0.50ix36548_ix913/O MUXF5 0.38 1.63 up 0.50ix36548_ix919/O MUXF6 0.24 1.86 up 0.50ix36548_ix933/O MUXF7 0.24 2.10 up 0.50ix36548_ix963/O MUXF8 0.24 2.34 up 0.80r_02(1)(6)/O LUT3 0.72 3.06 up 1.00nx14310/O LUT4 0.72 3.78 up 0.60modgen_xor_11683_nx2/O LUT4 0.72 4.50 up 0.50a(0)_dup_37693/O LUT4 0.72 5.22 up 1.00modgen_xor_11685_nx10/O LUT4 0.72 5.94 up 0.50modgen_xor_11685_ix13/LO LUT4_L 0.72 6.66 up 0.50nx40772/O LUT3 0.72 7.37 up 0.50next_round_data_2(0)(4)/O LUT4 0.72 8.09 up 0.60nx27520/O LUT4 0.72 8.81 up 0.60reg_s2_buf(0)(4)/D FDC 0.00 8.81 up 0.00data arrival time 8.81data required time (default specified - setup time) 8.94--------------------------------------------------------------------------------------------data required time 8.94data arrival time 8.81 ----------slack 0.13--------------------------------------------------------------------------------------------Critical path #3, (path slack = 0.1):NAME GATE ARRIVAL LOAD--------------------------------------------------------------------------------------------clock information not specifieddelay thru clock network 0.00 (ideal)reg_s3_buf(1)(1)/Q FDC 0.00 0.53 up 1.50ix36548_ix910/O LUT4 0.72 1.25 up 0.50ix36548_ix913/O MUXF5 0.38 1.63 up 0.50ix36548_ix919/O MUXF6 0.24 1.86 up 0.50ix36548_ix933/O MUXF7 0.24 2.10 up 0.50ix36548_ix963/O MUXF8 0.24 2.34 up 0.80r_02(1)(6)/O LUT3 0.72 3.06 up 1.00nx14310/O LUT4 0.72 3.78 up 0.60modgen_xor_11683_nx2/O LUT4 0.72 4.50 up 0.50a(0)_dup_37693/O LUT4 0.72 5.22 up 1.00modgen_xor_11685_nx10/O LUT4 0.72 5.94 up 0.50modgen_xor_11685_ix13/LO LUT4_L 0.72 6.66 up 0.50nx40772/O LUT3 0.72 7.37 up 0.50next_round_data_2(0)(4)/O LUT4 0.72 8.09 up 0.60nx27520/O LUT4 0.72 8.81 up 0.60reg_s2_buf(0)(4)/D FDC 0.00 8.81 up 0.00data arrival time 8.81data required time (default specified - setup time) 8.94--------------------------------------------------------------------------------------------data required time 8.94data arrival time 8.81 ----------slack 0.13--------------------------------------------------------------------------------------------Critical path #4, (path slack = 0.1):NAME GATE ARRIVAL LOAD--------------------------------------------------------------------------------------------clock information not specifieddelay thru clock network 0.00 (ideal)reg_s3_buf(1)(0)/Q FDC 0.00 0.53 up 1.50ix36548_ix910/O LUT4 0.72 1.25 up 0.50ix36548_ix913/O MUXF5 0.38 1.63 up 0.50ix36548_ix919/O MUXF6 0.24 1.86 up 0.50ix36548_ix933/O MUXF7 0.24 2.10 up 0.50ix36548_ix963/O MUXF8 0.24 2.34 up 0.80r_02(1)(6)/O LUT3 0.72 3.06 up 1.00nx14310/O LUT4 0.72 3.78 up 0.60modgen_xor_11683_nx2/O LUT4 0.72 4.50 up 0.50a(0)_dup_37693/O LUT4 0.72 5.22 up 1.00modgen_xor_11685_nx10/O LUT4 0.72 5.94 up 0.50modgen_xor_11685_ix13/LO LUT4_L 0.72 6.66 up 0.50nx40772/O LUT3 0.72 7.37 up 0.50next_round_data_2(0)(4)/O LUT4 0.72 8.09 up 0.60nx27520/O LUT4 0.72 8.81 up 0.60reg_s2_buf(0)(4)/D FDC 0.00 8.81 up 0.00data arrival time 8.81data required time (default specified - setup time) 8.94--------------------------------------------------------------------------------------------data required time 8.94data arrival time 8.81 ----------slack 0.13--------------------------------------------------------------------------------------------⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?