📄 main.map.rpt
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+------------------------+-------------------+----------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 5 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: FSK_demod:comb_7|Pulse_gen:comb_6|lpm_counter:count_rtl_2 ;
+------------------------+-------------------+---------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+---------------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 5 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Thu Nov 27 21:13:05 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Main -c Main
Info: Found 1 design units, including 1 entities, in source file encode.v
Info: Found entity 1: encode
Info: Found 1 design units, including 1 entities, in source file decode1.v
Info: Found entity 1: decode1
Info: Found 2 design units, including 2 entities, in source file FSK_mod.v
Info: Found entity 1: FSK_mod
Info: Found entity 2: MUX2x1
Info: Found 2 design units, including 2 entities, in source file FSK_demod.v
Info: Found entity 1: FSK_demod
Info: Found entity 2: Pulse_gen
Info: Found 1 design units, including 1 entities, in source file Main.v
Info: Found entity 1: Main
Info: Found 1 design units, including 1 entities, in source file clkgen.v
Info: Found entity 1: clkgen
Info: Found 1 design units, including 1 entities, in source file Freq_gen.v
Info: Found entity 1: Freq_gen
Critical Warning (10846): Verilog HDL Instantiation warning at FSK_mod.v(7): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at FSK_mod.v(8): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at FSK_demod.v(14): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at FSK_demod.v(15): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(12): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(13): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(14): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(15): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(18): instance has no name
Info: Elaborating entity "Main" for the top level hierarchy
Info: Elaborating entity "clkgen" for hierarchy "clkgen:comb_4"
Info: Elaborating entity "encode" for hierarchy "encode:comb_5"
Info: Elaborating entity "FSK_mod" for hierarchy "FSK_mod:comb_6"
Info: Elaborating entity "Freq_gen" for hierarchy "FSK_mod:comb_6|Freq_gen:comb_4"
Info: Elaborating entity "MUX2x1" for hierarchy "FSK_mod:comb_6|MUX2x1:comb_5"
Info: Elaborating entity "FSK_demod" for hierarchy "FSK_demod:comb_7"
Info: Elaborating entity "Pulse_gen" for hierarchy "FSK_demod:comb_7|Pulse_gen:comb_6"
Info: Elaborating entity "decode1" for hierarchy "decode1:comb_8"
Warning (10230): Verilog HDL assignment warning at decode1.v(62): truncated value with size 32 to match size of target (3)
Info: Inferred 3 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "clkgen:comb_4|count2[0]~5"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "FSK_demod:comb_7|count[0]~5"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "FSK_demod:comb_7|Pulse_gen:comb_6|count[0]~15"
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "clkgen:comb_4|lpm_counter:count2_rtl_0"
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "clkgen:comb_4|lpm_counter:count2_rtl_0"
Info: Instantiated megafunction "clkgen:comb_4|lpm_counter:count2_rtl_0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "5"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "FSK_demod:comb_7|lpm_counter:count_rtl_1"
Info: Elaborated megafunction instantiation "FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "FSK_demod:comb_7|lpm_counter:count_rtl_1"
Info: Instantiated megafunction "FSK_demod:comb_7|lpm_counter:count_rtl_1" with the following parameter:
Info: Parameter "LPM_WIDTH" = "5"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "FSK_demod:comb_7|Pulse_gen:comb_6|lpm_counter:count_rtl_2"
Info: Duplicate registers merged to single register
Info: Duplicate register "clkgen:comb_4|count1[0]" merged to single register "FSK_mod:comb_6|Freq_gen:comb_4|count1[0]"
Info: Duplicate register "clkgen:comb_4|count1[1]" merged to single register "FSK_mod:comb_6|Freq_gen:comb_4|count1[1]"
Info: State machine "|Main|encode:comb_5|step" contains 8 states
Info: Selected Auto state machine encoding method for state machine "|Main|encode:comb_5|step"
Info: Encoding result for state machine "|Main|encode:comb_5|step"
Info: Completed encoding using 8 state bits
Info: Encoded state bit "encode:comb_5|step.s7"
Info: Encoded state bit "encode:comb_5|step.s6"
Info: Encoded state bit "encode:comb_5|step.s5"
Info: Encoded state bit "encode:comb_5|step.s4"
Info: Encoded state bit "encode:comb_5|step.s3"
Info: Encoded state bit "encode:comb_5|step.s2"
Info: Encoded state bit "encode:comb_5|step.s1"
Info: Encoded state bit "encode:comb_5|step.s0"
Info: State "|Main|encode:comb_5|step.s0" uses code string "00000000"
Info: State "|Main|encode:comb_5|step.s1" uses code string "00000011"
Info: State "|Main|encode:comb_5|step.s2" uses code string "00000101"
Info: State "|Main|encode:comb_5|step.s3" uses code string "00001001"
Info: State "|Main|encode:comb_5|step.s4" uses code string "00010001"
Info: State "|Main|encode:comb_5|step.s5" uses code string "00100001"
Info: State "|Main|encode:comb_5|step.s6" uses code string "01000001"
Info: State "|Main|encode:comb_5|step.s7" uses code string "10000001"
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
Info: Register "encode:comb_5|step~10" lost all its fanouts during netlist optimizations.
Info: Register "encode:comb_5|step~11" lost all its fanouts during netlist optimizations.
Info: Register "encode:comb_5|step~12" lost all its fanouts during netlist optimizations.
Info: Implemented 70 device resources after synthesis - the final resource count might be different
Info: Implemented 6 input pins
Info: Implemented 5 output pins
Info: Implemented 59 logic cells
Info: Generated suppressed messages file D:/seventh term/通信原理实验/Main_mine/Main.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
Info: Allocated 136 megabytes of memory during processing
Info: Processing ended: Thu Nov 27 21:13:07 2008
Info: Elapsed time: 00:00:02
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/seventh term/通信原理实验/Main_mine/Main.map.smsg.
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