main.hier_info

模拟数字通信通道

|Main
clk_in => clk_in~0.IN3
rst => rst~0.IN2
in1 => in1~0.IN1
in2 => in2~0.IN1
in3 => in3~0.IN1
in4 => in4~0.IN1
out <= decode1:comb_8.out
FSK_out <= FSK_out~0.DB_MAX_OUTPUT_PORT_TYPE
wrong <= decode1:comb_8.wrong
DATA_in <= DATA_in~0.DB_MAX_OUTPUT_PORT_TYPE
DATA_out <= DATA_out~0.DB_MAX_OUTPUT_PORT_TYPE


|Main|clkgen:comb_4
clk_in => count1[2].CLK
clk_in => count1[1].CLK
clk_in => count1[0].CLK
clk_DATA <= count2[4].DB_MAX_OUTPUT_PORT_TYPE


|Main|encode:comb_5
clk => rom1.CLK
clk => rom2.CLK
clk => rom3.CLK
clk => rom4.CLK
clk => out~reg0.CLK
clk => checksum1.CLK
clk => checksum2.CLK
clk => checksum3.CLK
clk => step~0.IN1
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
in1 => rom1.DATAIN
in2 => rom2.DATAIN
in3 => rom3.DATAIN
in4 => rom4.DATAIN


|Main|FSK_mod:comb_6
clk_in => clk_in~0.IN1
rst => rst~0.IN1
DATA => DATA~0.IN1
FSK_out <= MUX2x1:comb_5.Dout


|Main|FSK_mod:comb_6|Freq_gen:comb_4
clk_in => count1[2].CLK
clk_in => count1[1].CLK
clk_in => count1[0].CLK
clk0 <= count2.DB_MAX_OUTPUT_PORT_TYPE
clk1 <= count1[2].DB_MAX_OUTPUT_PORT_TYPE


|Main|FSK_mod:comb_6|MUX2x1:comb_5
rst => Dout~3.IN0
A => Dout~0.IN0
A => Dout~1.IN0
D0 => Dout~1.IN1
D1 => Dout~0.IN1
Dout <= Dout~3.DB_MAX_OUTPUT_PORT_TYPE


|Main|FSK_demod:comb_7
clk_in => clk_in~0.IN1
clk_DATA => clk_DATA~0.IN1
FSK_receive => FSK_receive~0.IN1
DATA <= DATA_reg.DB_MAX_OUTPUT_PORT_TYPE


|Main|FSK_demod:comb_7|Freq_gen:comb_5
clk_in => count1[2].CLK
clk_in => count1[1].CLK
clk_in => count1[0].CLK
clk0 <= count2.DB_MAX_OUTPUT_PORT_TYPE
clk1 <= count1[2].DB_MAX_OUTPUT_PORT_TYPE


|Main|FSK_demod:comb_7|Pulse_gen:comb_6
clk_DATA => count~9.OUTPUTSELECT
clk_DATA => count~8.OUTPUTSELECT
clk_DATA => count~7.OUTPUTSELECT
clk_DATA => count~6.OUTPUTSELECT
clk_DATA => count~5.OUTPUTSELECT
frcv => count[4].CLK
frcv => count[3].CLK
frcv => count[2].CLK
frcv => count[1].CLK
frcv => count[0].CLK
pulse <= Equal0.DB_MAX_OUTPUT_PORT_TYPE


|Main|decode1:comb_8
clk => out~reg0.CLK
clk => checksum.CLK
clk => status[2].CLK
clk => status[1].CLK
clk => status[0].CLK
clk => wrong~reg0.CLK
clr => wrong~reg0.ENA
clr => status[0].ENA
clr => status[1].ENA
clr => status[2].ENA
clr => checksum.ENA
clr => out~reg0.ENA
in => status~5.DATAB
in => status~4.DATAB
in => status~7.DATAB
in => status~11.DATAB
in => out~0.DATAB
in => always0~3.IN1
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
wrong <= wrong~reg0.DB_MAX_OUTPUT_PORT_TYPE