prev_cmp_main.map.qmsg

模拟数字通信通道

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 27 21:08:11 2008 " "Info: Processing started: Thu Nov 27 21:08:11 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Main -c Main " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Main -c Main" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "encode.v(16) " "Warning (10268): Verilog HDL information at encode.v(16): Always Construct contains both blocking and non-blocking assignments" {  } { { "encode.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/encode.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "encode.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file encode.v" { { "Info" "ISGN_ENTITY_NAME" "1 encode " "Info: Found entity 1: encode" {  } { { "encode.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/encode.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decode1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file decode1.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode1 " "Info: Found entity 1: decode1" {  } { { "decode1.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/decode1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FSK_mod.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file FSK_mod.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSK_mod " "Info: Found entity 1: FSK_mod" {  } { { "FSK_mod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_mod.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 MUX2x1 " "Info: Found entity 2: MUX2x1" {  } { { "FSK_mod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_mod.v" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FSK_demod.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file FSK_demod.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSK_demod " "Info: Found entity 1: FSK_demod" {  } { { "FSK_demod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_demod.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 Pulse_gen " "Info: Found entity 2: Pulse_gen" {  } { { "FSK_demod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_demod.v" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Main.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Main.v" { { "Info" "ISGN_ENTITY_NAME" "1 Main " "Info: Found entity 1: Main" {  } { { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkgen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkgen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkgen " "Info: Found entity 1: clkgen" {  } { { "clkgen.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/clkgen.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Freq_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Freq_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 Freq_gen " "Info: Found entity 1: Freq_gen" {  } { { "Freq_gen.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Freq_gen.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "FSK_mod.v(7) " "Critical Warning (10846): Verilog HDL Instantiation warning at FSK_mod.v(7): instance has no name" {  } { { "FSK_mod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_mod.v" 7 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "FSK_mod.v(8) " "Critical Warning (10846): Verilog HDL Instantiation warning at FSK_mod.v(8): instance has no name" {  } { { "FSK_mod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_mod.v" 8 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "FSK_demod.v(14) " "Critical Warning (10846): Verilog HDL Instantiation warning at FSK_demod.v(14): instance has no name" {  } { { "FSK_demod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_demod.v" 14 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "FSK_demod.v(15) " "Critical Warning (10846): Verilog HDL Instantiation warning at FSK_demod.v(15): instance has no name" {  } { { "FSK_demod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_demod.v" 15 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "Main.v(12) " "Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(12): instance has no name" {  } { { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 12 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "Main.v(13) " "Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(13): instance has no name" {  } { { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 13 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "Main.v(14) " "Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(14): instance has no name" {  } { { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 14 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "Main.v(15) " "Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(15): instance has no name" {  } { { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 15 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "Main.v(18) " "Critical Warning (10846): Verilog HDL Instantiation warning at Main.v(18): instance has no name" {  } { { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 18 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Main " "Info: Elaborating entity \"Main\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkgen clkgen:comb_4 " "Info: Elaborating entity \"clkgen\" for hierarchy \"clkgen:comb_4\"" {  } { { "Main.v" "comb_4" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 12 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "encode encode:comb_5 " "Info: Elaborating entity \"encode\" for hierarchy \"encode:comb_5\"" {  } { { "Main.v" "comb_5" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 13 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSK_mod FSK_mod:comb_6 " "Info: Elaborating entity \"FSK_mod\" for hierarchy \"FSK_mod:comb_6\"" {  } { { "Main.v" "comb_6" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 14 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Freq_gen FSK_mod:comb_6\|Freq_gen:comb_4 " "Info: Elaborating entity \"Freq_gen\" for hierarchy \"FSK_mod:comb_6\|Freq_gen:comb_4\"" {  } { { "FSK_mod.v" "comb_4" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_mod.v" 7 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}