prev_cmp_main.tan.qmsg

模拟数字通信通道

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_in 63 " "Warning: Circuit may not operate. Detected 63 non-operational path(s) clocked by clock \"clk_in\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] clk_in 12.7 ns " "Info: Found hold time violation between source  pin or register \"FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]\" and destination pin or register \"FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]\" for clock \"clk_in\" (Hold time is 12.7 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "14.200 ns + Largest " "Info: + Largest clock skew is 14.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 25.800 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to destination register is 25.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk_in 1 CLK PIN_91 4 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_91; Fanout = 4; CLK Node = 'clk_in'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.900 ns) 5.800 ns clkgen:comb_4\|count1\[2\] 2 REG LC1_E28 6 " "Info: 2: + IC(2.700 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC1_E28; Fanout = 6; REG Node = 'clkgen:comb_4\|count1\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk_in clkgen:comb_4|count1[2] } "NODE_NAME" } } { "clkgen.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/clkgen.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.900 ns) 9.000 ns clkgen:comb_4\|lpm_counter:count2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 3 REG LC1_E21 25 " "Info: 3: + IC(2.300 ns) + CELL(0.900 ns) = 9.000 ns; Loc. = LC1_E21; Fanout = 25; REG Node = 'clkgen:comb_4\|lpm_counter:count2_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { clkgen:comb_4|count1[2] clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.800 ns) + CELL(0.900 ns) 16.700 ns encode:comb_5\|out 4 REG LC3_E7 1 " "Info: 4: + IC(6.800 ns) + CELL(0.900 ns) = 16.700 ns; Loc. = LC3_E7; Fanout = 1; REG Node = 'encode:comb_5\|out'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[4] encode:comb_5|out } "NODE_NAME" } } { "encode.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/encode.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(1.900 ns) 22.200 ns FSK_mod:comb_6\|MUX2x1:comb_5\|Dout~52 5 COMB LC4_E28 10 " "Info: 5: + IC(3.600 ns) + CELL(1.900 ns) = 22.200 ns; Loc. = LC4_E28; Fanout = 10; COMB Node = 'FSK_mod:comb_6\|MUX2x1:comb_5\|Dout~52'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { encode:comb_5|out FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 } "NODE_NAME" } } { "FSK_mod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_mod.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.000 ns) 25.800 ns FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 6 REG LC3_B19 4 " "Info: 6: + IC(3.600 ns) + CELL(0.000 ns) = 25.800 ns; Loc. = LC3_B19; Fanout = 4; REG Node = 'FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.800 ns ( 26.36 % ) " "Info: Total cell delay = 6.800 ns ( 26.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "19.000 ns ( 73.64 % ) " "Info: Total interconnect delay = 19.000 ns ( 73.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "25.800 ns" { clk_in clkgen:comb_4|count1[2] clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[4] encode:comb_5|out FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "25.800 ns" { clk_in {} clk_in~out {} clkgen:comb_4|count1[2] {} clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[4] {} encode:comb_5|out {} FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 {} FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.700ns 2.300ns 6.800ns 3.600ns 3.600ns } { 0.000ns 2.200ns 0.900ns 0.900ns 0.900ns 1.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 11.600 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to source register is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk_in 1 CLK PIN_91 4 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_91; Fanout = 4; CLK Node = 'clk_in'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.900 ns) 5.800 ns FSK_mod:comb_6\|Freq_gen:comb_4\|count1\[2\] 2 REG LC2_E28 3 " "Info: 2: + IC(2.700 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC2_E28; Fanout = 3; REG Node = 'FSK_mod:comb_6\|Freq_gen:comb_4\|count1\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk_in FSK_mod:comb_6|Freq_gen:comb_4|count1[2] } "NODE_NAME" } } { "Freq_gen.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Freq_gen.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.900 ns) 8.000 ns FSK_mod:comb_6\|MUX2x1:comb_5\|Dout~52 3 COMB LC4_E28 10 " "Info: 3: + IC(0.300 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC4_E28; Fanout = 10; COMB Node = 'FSK_mod:comb_6\|MUX2x1:comb_5\|Dout~52'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { FSK_mod:comb_6|Freq_gen:comb_4|count1[2] FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 } "NODE_NAME" } } { "FSK_mod.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/FSK_mod.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.000 ns) 11.600 ns FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 4 REG LC3_B19 4 " "Info: 4: + IC(3.600 ns) + CELL(0.000 ns) = 11.600 ns; Loc. = LC3_B19; Fanout = 4; REG Node = 'FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 43.10 % ) " "Info: Total cell delay = 5.000 ns ( 43.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns ( 56.90 % ) " "Info: Total interconnect delay = 6.600 ns ( 56.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { clk_in FSK_mod:comb_6|Freq_gen:comb_4|count1[2] FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { clk_in {} clk_in~out {} FSK_mod:comb_6|Freq_gen:comb_4|count1[2] {} FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 {} FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.700ns 0.300ns 3.600ns } { 0.000ns 2.200ns 0.900ns 1.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "25.800 ns" { clk_in clkgen:comb_4|count1[2] clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[4] encode:comb_5|out FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "25.800 ns" { clk_in {} clk_in~out {} clkgen:comb_4|count1[2] {} clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[4] {} encode:comb_5|out {} FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 {} FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.700ns 2.300ns 6.800ns 3.600ns 3.600ns } { 0.000ns 2.200ns 0.900ns 0.900ns 0.900ns 1.900ns 0.000ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { clk_in FSK_mod:comb_6|Freq_gen:comb_4|count1[2] FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { clk_in {} clk_in~out {} FSK_mod:comb_6|Freq_gen:comb_4|count1[2] {} FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 {} FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.700ns 0.300ns 3.600ns } { 0.000ns 2.200ns 0.900ns 1.900ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns - " "Info: - Micro clock to output delay of source is 0.900 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns - Shortest register register " "Info: - Shortest register to register delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 1 REG LC3_B19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B19; Fanout = 4; REG Node = 'FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC3_B19 4 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = LC3_B19; Fanout = 4; REG Node = 'FSK_demod:comb_7\|lpm_counter:count_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns } { 0.000ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "25.800 ns" { clk_in clkgen:comb_4|count1[2] clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[4] encode:comb_5|out FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "25.800 ns" { clk_in {} clk_in~out {} clkgen:comb_4|count1[2] {} clkgen:comb_4|lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[4] {} encode:comb_5|out {} FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 {} FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.700ns 2.300ns 6.800ns 3.600ns 3.600ns } { 0.000ns 2.200ns 0.900ns 0.900ns 0.900ns 1.900ns 0.000ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { clk_in FSK_mod:comb_6|Freq_gen:comb_4|count1[2] FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { clk_in {} clk_in~out {} FSK_mod:comb_6|Freq_gen:comb_4|count1[2] {} FSK_mod:comb_6|MUX2x1:comb_5|Dout~52 {} FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.700ns 0.300ns 3.600ns } { 0.000ns 2.200ns 0.900ns 1.900ns 0.000ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} FSK_demod:comb_7|lpm_counter:count_rtl_1|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns } { 0.000ns 1.500ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "decode1:comb_8\|wrong rst clk_in -2.800 ns register " "Info: tsu for register \"decode1:comb_8\|wrong\" (data pin = \"rst\", clock pin = \"clk_in\") is -2.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.600 ns + Longest pin register " "Info: + Longest pin to register delay is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns rst 1 CLK PIN_210 3 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_210; Fanout = 3; CLK Node = 'rst'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.400 ns) 6.400 ns decode1:comb_8\|wrong~48 2 COMB LC5_B22 1 " "Info: 2: + IC(2.800 ns) + CELL(1.400 ns) = 6.400 ns; Loc. = LC5_B22; Fanout = 1; COMB Node = 'decode1:comb_8\|wrong~48'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.200 ns" { rst decode1:comb_8|wrong~48 } "NODE_NAME" } } { "decode1.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/decode1.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.900 ns) 10.400 ns decode1:comb_8\|wrong~49 3 COMB LC3_B26 1 " "Info: 3: + IC(2.100 ns) + CELL(1.900 ns) = 10.400 ns; Loc. = LC3_B26; Fanout = 1; COMB Node = 'decode1:comb_8\|wrong~49'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { decode1:comb_8|wrong~48 decode1:comb_8|wrong~49 } "NODE_NAME" } } { "decode1.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/decode1.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.900 ns) 11.600 ns decode1:comb_8\|wrong 4 REG LC4_B26 2 " "Info: 4: + IC(0.300 ns) + CELL(0.900 ns) = 11.600 ns; Loc. = LC4_B26; Fanout = 2; REG Node = 'decode1:comb_8\|wrong'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { decode1:comb_8|wrong~49 decode1:comb_8|wrong } "NODE_NAME" } } { "decode1.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/decode1.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns ( 55.17 % ) " "Info: Total cell delay = 6.400 ns ( 55.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns ( 44.83 % ) " "Info: Total interconnect delay = 5.200 ns ( 44.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { rst decode1:comb_8|wrong~48 decode1:comb_8|wrong~49 decode1:comb_8|wrong } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { rst {} rst~out {} decode1:comb_8|wrong~48 {} decode1:comb_8|wrong~49 {} decode1:comb_8|wrong {} } { 0.000ns 0.000ns 2.800ns 2.100ns 0.300ns } { 0.000ns 2.200ns 1.400ns 1.900ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.400 ns + " "Info: + Micro setup delay of destination is 1.400 ns" {  } { { "decode1.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/decode1.v" 4 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 15.800 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to destination register is 15.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk_in 1 CLK PIN_91 4 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_91; Fanout = 4; CLK Node = 'clk_in'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Main.v" "" { Text "D:/seventh term/通信原理实验/Main_mine/Main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.900 ns) 5.800 ns clkgen:comb_4\|count1\[2\] 2 REG LC1_E28 6 " "Info: 2: + IC(2.700 ns) + CELL(0.900 ns) = 5.800 ns; Loc. = LC1_E2