main.map.summary

模拟数字通信通道

Analysis & Synthesis Status : Successful - Thu Nov 27 21:13:07 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : Main
Top-level Entity Name : Main
Family : FLEX10K
Total logic elements : 59
Total pins : 11
Total memory bits : 0