decode1.v

来自「模拟数字通信通道」· Verilog 代码 · 共 77 行

module decode1(clk,clr,in,out,wrong);

input clk,clr,in;
output out,wrong;

//reg [1:0] step;
reg [2:0] status;
reg checksum;
reg out,wrong;

initial
begin
status<=3'b000;
checksum<=0;
wrong<=0;
end

always @ (posedge clk)
begin
if(clr==0)
   begin
   if(status==3'b000)
      begin
      out<=0;
checksum<=0;
      if(in==1)
         begin
         status<=3'b001;
         end
      else
         begin
         status<=3'b000;
         end
      end
   else if(status==3'b001)
      begin
      out<=0;
      if(in==1)
         begin
         status<=3'b010;
         end
      else
         begin
         status<=3'b000;
         end
      end
    else if(status==3'b010)
       begin
       out<=0;
       if(in==1)
          begin
          status<=3'b011;
          end
       else
          begin
          status<=3'b000;
          end
       end
    else if(status==3'b011 || status==3'b100 || status==3'b101 || status==3'b110)
       begin
       out<=in;
       status<=status+1;
       checksum<=checksum^in;
       end
    else
       begin
       out<=0;
       status<=3'b000;
       if(checksum!=in)
          begin
          wrong<=!wrong;
          end
       end
end
end               
endmodule