freq_gen.v

来自「模拟数字通信通道」· Verilog 代码 · 共 79 行

module Freq_gen(clk_in,clk0,clk1);

	input clk_in;
	output clk0,clk1;
	reg [2:0] count1;
	reg count2;
	
	assign clk0=count2;
	assign clk1=count1[2];
	
	initial
	begin
		count1<=3'b000;
		count2<=1'b0;
	end
	
	always@(posedge clk_in)
	begin
		if (count1==3'b111)
			count1<=3'b000;
		else
		begin
			count1<=count1+3'b001;
		end
	end
	
	always@(posedge count1[2])
	begin
		if (count2==1'b1)
			count2<=1'b0;
		else
			count2<=count2+1'b1;
	end
	
endmodule
/*	
module Freq_gen(clk_in,clk0,clk1);

	input clk_in;
	output clk0,clk1;
	reg [2:0] count;
//	reg clk_h;
	
//	assign clk_h=count[2];
	
	initial
	begin
		count<=3'b000;
	end

	always@(posedge clk_in)
	begin
		if (count==8'b111)
			count<=8'b000;
		else
			count<=count+8'b001;
	end
	
	reg [1:0] count1;
	
	assign clk0=count1[1];
	assign clk1=count1[0];
	
	initial
	begin
		count1<=2'b00;
	end
	
	always@(posedge count[2])
	begin
		if (count==2'b11)
			count<=2'b00;
		else
		begin
			count<=count+2'b01;
		end
	end
	
endmodule*/