encode.v

来自「模拟数字通信通道」· Verilog 代码 · 共 63 行

module encode(clk,out,in1,in2,in3,in4);

input clk,in1,in2,in3,in4;
output out;

reg [2:0] step;
reg checksum1,checksum2,checksum3,rom1,rom2,rom3,rom4;
reg out;
parameter s0 = 3'b000,s1 = 3'b001, s2 = 3'b010,s3 = 3'b011, s4 = 3'b100,s5 = 3'b101,s6 = 3'b110,s7 = 3'b111;

initial
begin
    step<=s0;
end

always @ (posedge clk)
begin 
    case(step)
    s0: begin
        rom1<=in1;
        rom2<=in2;
        rom3<=in3;
        rom4<=in4;
        out<=1;
        step<=s1;
        end
    s1: begin
        out<=1;
        step<=s2;
        end
    s2: begin
        out<=1;
        step<=s3;
        end
    s3: begin
        out<=rom1;
        step<=s4;
        end
    s4: begin
        out<=rom2;
        //xor x1(checksum1,rom1,rom2);
        checksum1=rom1^rom2;
        step<=s5;
        end
    s5: begin
        out<=rom3;
        //xor x2(checksum2,checksum1,rom3);
		checksum2<=checksum1^rom3;
        step<=s6;
        end
    s6: begin
        out<=rom4;
        //xor x3(checksum3,checksum2,rom4);
        checksum3=checksum2^rom4;
        step<=s7;
        end
    s7: begin
        out<=checksum3;
        step<=s0;
        end
endcase
end
endmodule