fsk_demod.v

来自「模拟数字通信通道」· Verilog 代码 · 共 56 行

module FSK_demod(clk_in,clk_DATA,FSK_receive,DATA);
//,psk_rst,count);

	input clk_in,clk_DATA,FSK_receive;
	output DATA;
	//output psk_rst,count;	//temp
	wire clk0,clk1;
	wire psk_rst;
	reg DATA_reg;
	reg [4:0] count;

	assign DATA=DATA_reg;
	//assign psk_rst=pulse;
	Freq_gen(.clk_in(clk_in),.clk0(clk0),.clk1(clk1));	//rebuild clk0 and clk1
	Pulse_gen(.clk_DATA(clk_DATA),.frcv(FSK_receive),.pulse(psk_rst));

	always@(posedge clk_DATA)
	begin
		if(count<=5'b10101)	//5'b10110=22
			DATA_reg<=1'b0;
		else
			DATA_reg<=1'b1;
	end	
	
	always@(posedge FSK_receive)
	begin
		if (psk_rst)
			count<=5'b00000;
		else
			count<=count+5'b00001;
	end
	
endmodule

module Pulse_gen(clk_DATA,frcv,pulse);

	input clk_DATA,frcv;
	output pulse;
	reg [4:0] count;
	
	assign pulse=(count==5'b00001);
	
	always@(posedge frcv)
	begin
		if (!clk_DATA)
			count<=5'b00000;
		else
		begin	
			if (count==5'b11111)
				count<=5'b00000;
			else
				count<=count+5'b00001;
		end
	end

endmodule