clkgen.v.bak

模拟数字通信通道

module clkgen(clk_in,clk_DATA);

	input clk_in;
	output clk_DATA;
//	reg clk_h;
	reg [2:0] count;
	reg [4:0] count1;
	
//	assign clk_h=count[2];
	initial
	begin
		count<=3'b000;
	end

	always@(posedge clk_in)
	begin
		if (count==8'b111)
			count<=8'b000;
		else
			count<=count+8'b001;
	end
	
	assign clk_DATA=count1[4];	
	initial
	begin
		count1<=8'b00000;
	end
	
	always@(posedge count[2])
	begin
		if (count1==8'b11111)
			count1<=8'b00000;
		else
			count1<=count1+8'b00001;
	end
	
endmodule