wb_lpc_host.v

Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read a

                        adr_cnt <= adr_cnt + 1;
                        
                        if(adr_cnt == 4'h7) // Last address nibble.
                            begin
                                if(~fw_xfr)
                                    if(wbs_wr)
                                        state <= `LPC_ST_H_DATA;
                                    else
                                        state <= `LPC_ST_H_TAR1;
                                else    // For firmware read/write, we need to transfer the MSIZE nibble
                                    state <= `LPC_ST_SIZE;
                            end
                        else
                            state <= `LPC_ST_ADDR;
        
                        lad_oe  <= 1'b1;
                        xfr_len     <= 3'b001;      // One Byte Transfer
                    end
                `LPC_ST_CHAN:
                    begin
                        lad_o   <= {dma_tc_i, dma_chan_i};
                        state <= `LPC_ST_SIZE;
                    end
                `LPC_ST_SIZE:
                    begin
                        case(wbs_sel_i)
                            `WB_SEL_BYTE:
                                begin
                                    xfr_len <= 3'b001;
                                    lad_o <= 4'h0;
                                end
                            `WB_SEL_SHORT:
                                begin
                                    xfr_len <= 3'b010;
                                    lad_o <= 4'h1;
                                end
                            `WB_SEL_WORD:
                                begin
                                    xfr_len <= 3'b100;
                                    if(fw_xfr)              // Firmware transfer uses '2' for 4-byte transfer.
                                        lad_o <= 4'h2;
                                    else                    // DMA uses '3' for 4-byte transfer.
                                        lad_o <= 4'h3;
                                end
                            default:
                                begin
                                    xfr_len <= 3'b001;
                                    lad_o <= 4'h0;
                                end
                        endcase
                        if(wbs_wr)
                            state <= `LPC_ST_H_DATA;
                        else
                            state <= `LPC_ST_H_TAR1;
                    end

                `LPC_ST_H_DATA:
                    begin
                        lad_oe  <= 1'b1;
                        case(dat_cnt)   // We only support a single byte for I/O.
                            4'h0:
                                lad_o <= wbs_dat_i[3:0];
                            4'h1:
                                lad_o <= wbs_dat_i[7:4];
                            4'h2:
                                lad_o <= wbs_dat_i[11:8];
                            4'h3:
                                lad_o <= wbs_dat_i[15:12];
                            4'h4:
                                lad_o <= wbs_dat_i[19:16];
                            4'h5:
                                lad_o <= wbs_dat_i[23:20];
                            4'h6:
                                lad_o <= wbs_dat_i[27:24];
                            4'h7:
                                lad_o <= wbs_dat_i[31:28];
                            default:
                                lad_o <= 4'hx;
                        endcase
                        
                        dat_cnt <= dat_cnt + 1;
                        
                        if(nibble_cnt == 1'b1) // end of byte
                            begin
                                if((fw_xfr) && (byte_cnt != xfr_len-1)) // Firmware transfer does not have TAR between bytes.
                                    state <= `LPC_ST_H_DATA;
                                else
                                    state <= `LPC_ST_H_TAR1;
                            end
                        else
                            state <= `LPC_ST_H_DATA;
                    end
        
                `LPC_ST_H_TAR1:
                    begin
                        lad_o <= 4'b1111;       // Drive LAD high
                        lad_oe <= 1'b1;
                        state <= `LPC_ST_H_TAR2;
                    end
                `LPC_ST_H_TAR2:
                    begin
                        lad_oe <= 1'b0;     // float LAD
                        state <= `LPC_ST_SYNC;
                    end
                `LPC_ST_SYNC:
                    begin
                        lad_oe <= 1'b0;     // float LAD
                        if((lad_i == `LPC_SYNC_READY) || (lad_i == `LPC_SYNC_MORE)) begin
                            if(wbs_wr) begin
                                state <= `LPC_ST_P_TAR1;
                            end
                            else begin
                                state <= `LPC_ST_P_DATA;
                            end
                        end else if(lad_i == `LPC_SYNC_ERROR) begin
                            dat_cnt <= { xfr_len, 1'b1 };    // Terminate data transfer
                            wbs_err_o <= 1'b1;    // signal wishbone error
                            state <= `LPC_ST_P_TAR1;
                        end else begin
                            state <= `LPC_ST_SYNC;
                        end
                    end
        
                `LPC_ST_P_DATA:
                    begin
                        case(dat_cnt)
                            4'h0:
                                lpc_dat_i[3:0] <= lad_i;
                            4'h1:
                                lpc_dat_i[7:4] <= lad_i;
                            4'h2:
                                lpc_dat_i[11:8] <= lad_i;
                            4'h3:
                                lpc_dat_i[15:12] <= lad_i;
                            4'h4:
                                lpc_dat_i[19:16] <= lad_i;
                            4'h5:
                                lpc_dat_i[23:20] <= lad_i;
                            4'h6:
                                lpc_dat_i[27:24] <= lad_i;
                            4'h7:
                                lpc_dat_i[31:28] <= lad_i;
                        endcase
                        
                        dat_cnt <= dat_cnt + 1;
                        
                        if(nibble_cnt == 1'b1)          // Byte transfer complete
                            if (byte_cnt == xfr_len-1)  // End of data transfer phase
                                state <= `LPC_ST_P_TAR1;
                            else begin
                                if(fw_xfr) // Firmware transfer does not have TAR between bytes.
                                    state <= `LPC_ST_P_DATA;
                                else
                                    state <= `LPC_ST_SYNC;
                            end
                        else                            // Go to next nibble
                            state <= `LPC_ST_P_DATA;
                    end
                `LPC_ST_P_TAR1:
                    begin
                        lad_oe <= 1'b0;
                        if(byte_cnt == xfr_len) begin
                            state <= `LPC_ST_WB_RETIRE;
                            wbs_ack_o <= wbs_acc;
                        end
                        else begin
                            if(wbs_wr) begin    // DMA READ (Host to Peripheral)
                                state <= `LPC_ST_H_DATA;
                            end
                            else begin  // unhandled READ case
                                state <= `LPC_ST_IDLE;
                            end
                        end
                    end
                `LPC_ST_WB_RETIRE:
                    begin
                        wbs_ack_o <= 1'b0;
                        wbs_err_o <= 1'b0;
                        if(wbs_acc) begin
                            state <= `LPC_ST_WB_RETIRE;
                        end
                        else begin
                            state <= `LPC_ST_IDLE;
                        end
                    end
            endcase
        end

endmodule