lpc_7seg.ucf

Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read a

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "DISP_LED<0>"  LOC = "AB20" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_LED<1>"  LOC = "AA20" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_LED<2>"  LOC = "V18" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_LED<3>"  LOC = "Y17" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_LED<4>"  LOC = "AB18" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_LED<5>"  LOC = "AA18" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_LED<6>"  LOC = "W18" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_SEL<0>"  LOC = "AA17" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_SEL<1>"  LOC = "U17" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_SEL<2>"  LOC = "U16" | IOSTANDARD = LVCMOS33 ; 
NET "DISP_SEL<3>"  LOC = "U14" | IOSTANDARD = LVCMOS33 ; 
NET "LAD<0>"  LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW  | IOBDELAY = BOTH | KEEPER ;
NET "LAD<1>"  LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW  | IOBDELAY = BOTH | KEEPER ;
NET "LAD<2>"  LOC = "V2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW  | IOBDELAY = BOTH | KEEPER ;
NET "LAD<3>"  LOC = "V1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW  | IOBDELAY = BOTH | KEEPER ;
NET "LAD_OE"  LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = FAST  | DRIVE = 12 ; 
NET "LFRAME"  LOC = "W2" | IOSTANDARD = LVCMOS33 ;
NET "LPC_CLK"  LOC = "W1" | IOSTANDARD = LVCMOS33 ; 
NET "RST"  LOC = "A19" | IOSTANDARD = PCI33_3 ; 

# Update for ISE 10.1, which complains about this.
NET "LPC_CLK" CLOCK_DEDICATED_ROUTE = FALSE;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE