uart_stim.dat

Implements a 16550/16750 UART core

#WR 011 00010110
#RD 011 00010110
#WAIT 6944
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x17
#WR 011 00010111
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3761
#WR 000 01010101
#WAIT 3761
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 01010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3761
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3761
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 10101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01010111
#RD 011 01010111
#WAIT 7523
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00010111
#RD 011 00010111
#WAIT 7523
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x18
#WR 011 00011000
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 2893
#WR 000 01010101
#WAIT 2893
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 2893
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 2893
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00001010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01011000
#RD 011 01011000
#WAIT 5787
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00011000
#RD 011 00011000
#WAIT 5787
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x19
#WR 011 00011001
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3182
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3182
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01011001
#RD 011 01011001
#WAIT 6365
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00011001
#RD 011 00011001
#WAIT 6365
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x1A
#WR 011 00011010
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3472
#WR 000 01010101
#WAIT 3472
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 01010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3472
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3472
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01011010
#RD 011 01011010
#WAIT 6944
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00011010
#RD 011 00011010
#WAIT 6944
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x1B
#WR 011 00011011
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3761
#WR 000 01010101
#WAIT 3761
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 01010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3761
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3761
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 10101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01011011
#RD 011 01011011
#WAIT 7523
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00011011
#RD 011 00011011
#WAIT 7523
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x1C
#WR 011 00011100
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3182
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3182
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Br