📄 uart_stim.dat
字号:
#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010001#RD 011 01010001#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010001#RD 011 00010001#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x12#WR 011 00010010#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010010#RD 011 01010010#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010010#RD 011 00010010#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x13#WR 011 00010011#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 10101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010011#RD 011 01010011#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010011#RD 011 00010011#WAIT 6944#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x14#WR 011 00010100#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 2893#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 2893#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 2893#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 2893#RD 010 00000100#RD 101 01100001#RD 000 00001010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010100#RD 011 01010100#WAIT 5787#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010100#RD 011 00010100#WAIT 5787#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x15#WR 011 00010101#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3182#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 00010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3182#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3182#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3182#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010101#RD 011 01010101#WAIT 6365#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000#WR 011 00010101#RD 011 00010101#WAIT 6365#RD 101 01100000#RD 010 00000001#LOG UART: Setting LCR to 0x16#WR 011 00010110#LOG UART: Transmission test single byte (FIFO disabled)#WAIT 3472#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#RD 101 01100001#RD 000 01010101#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Transmission test multiple bytes (FIFO disabled)#RD 010 00000001#WR 000 00000000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000001#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000010#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000010#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000011#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000011#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000100#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000101#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000101#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000110#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000110#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00000111#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00000111#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001000#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001000#RD 010 00000010#RD 101 01100000#RD 010 00000001#WR 000 00001001#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00001001#RD 010 00000010#RD 101 01100000#LOG UART: Transmission test overflow (FIFO disabled)#WR 000 01010101#WAIT 3472#RD 101 01100001#RD 010 00000100#WR 000 10101010#WAIT 3472#RD 010 00000110#RD 101 01100011#RD 010 00000100#WAIT 3472#RD 010 00000100#RD 101 01100001#RD 000 00101010#RD 101 01100000#RD 010 00000010#RD 010 00000001#LOG UART: Break control test#WR 011 01010110#RD 011 01010110#WAIT 6944#RD 010 00000110#RD 101 01111001#RD 010 00000100#RD 101 01100001#RD 000 00000000#RD 010 00000001#RD 101 01100000⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -