uart_stim.dat

Implements a 16550/16750 UART core

#RD 000 01010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3761
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3761
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 10101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01001011
#RD 011 01001011
#WAIT 7523
#RD 010 00000110
#RD 101 01111101
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00001011
#RD 011 00001011
#WAIT 7523
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x0C
#WR 011 00001100
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3182
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3182
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01001100
#RD 011 01001100
#WAIT 6365
#RD 010 00000110
#RD 101 01111101
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00001100
#RD 011 00001100
#WAIT 6365
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x0D
#WR 011 00001101
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3472
#WR 000 01010101
#WAIT 3472
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3472
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3472
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01001101
#RD 011 01001101
#WAIT 6944
#RD 010 00000110
#RD 101 01111101
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00001101
#RD 011 00001101
#WAIT 6944
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x0E
#WR 011 00001110
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3761
#WR 000 01010101
#WAIT 3761
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 01010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3761
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3761
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3761
#RD 010 00000100
#RD 101 01100001
#RD 000 00101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01001110
#RD 011 01001110
#WAIT 7523
#RD 010 00000110
#RD 101 01111101
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00001110
#RD 011 00001110
#WAIT 7523
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x0F
#WR 011 00001111
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 4050
#WR 000 01010101
#WAIT 4050
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 01010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 4050
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 4050
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 4050
#RD 010 00000100
#RD 101 01100001
#RD 000 10101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01001111
#RD 011 01001111
#WAIT 8101
#RD 010 00000110
#RD 101 01111101
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00001111
#RD 011 00001111
#WAIT 8101
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x10
#WR 011 00010000
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 2604
#WR 000 01010101
#WAIT 2604
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 2604
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 2604
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00001010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01010000
#RD 011 01010000
#WAIT 5208
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00010000
#RD 011 00010000
#WAIT 5208
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x11
#WR 011 00010001