prev_cmp_tingchechang.tan.qmsg

停车场显示是日常生活中使用很平常的系统

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 -32 136 32 "clk" "" } } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register tingche:inst1\|l_num\[2\] register tingche:inst1\|q\[1\] 183.96 MHz 5.436 ns Internal " "Info: Clock \"clk\" has Internal fmax of 183.96 MHz between source register \"tingche:inst1\|l_num\[2\]\" and destination register \"tingche:inst1\|q\[1\]\" (period= 5.436 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.204 ns + Longest register register " "Info: + Longest register to register delay is 5.204 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tingche:inst1\|l_num\[2\] 1 REG LC_X11_Y12_N4 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N4; Fanout = 16; REG Node = 'tingche:inst1\|l_num\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { tingche:inst1|l_num[2] } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.590 ns) + CELL(0.442 ns) 1.032 ns tingche:inst1\|tmp~18034 2 COMB LC_X11_Y12_N1 14 " "Info: 2: + IC(0.590 ns) + CELL(0.442 ns) = 1.032 ns; Loc. = LC_X11_Y12_N1; Fanout = 14; COMB Node = 'tingche:inst1\|tmp~18034'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.032 ns" { tingche:inst1|l_num[2] tingche:inst1|tmp~18034 } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.274 ns) + CELL(0.442 ns) 2.748 ns tingche:inst1\|tmp~18081 3 COMB LC_X10_Y14_N7 1 " "Info: 3: + IC(1.274 ns) + CELL(0.442 ns) = 2.748 ns; Loc. = LC_X10_Y14_N7; Fanout = 1; COMB Node = 'tingche:inst1\|tmp~18081'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.716 ns" { tingche:inst1|tmp~18034 tingche:inst1|tmp~18081 } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.292 ns) 3.478 ns tingche:inst1\|Mux6~37 4 COMB LC_X10_Y14_N1 1 " "Info: 4: + IC(0.438 ns) + CELL(0.292 ns) = 3.478 ns; Loc. = LC_X10_Y14_N1; Fanout = 1; COMB Node = 'tingche:inst1\|Mux6~37'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { tingche:inst1|tmp~18081 tingche:inst1|Mux6~37 } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.114 ns) 4.288 ns tingche:inst1\|Mux6~38 5 COMB LC_X9_Y14_N8 1 " "Info: 5: + IC(0.696 ns) + CELL(0.114 ns) = 4.288 ns; Loc. = LC_X9_Y14_N8; Fanout = 1; COMB Node = 'tingche:inst1\|Mux6~38'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { tingche:inst1|Mux6~37 tingche:inst1|Mux6~38 } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.478 ns) 5.204 ns tingche:inst1\|q\[1\] 6 REG LC_X9_Y14_N4 1 " "Info: 6: + IC(0.438 ns) + CELL(0.478 ns) = 5.204 ns; Loc. = LC_X9_Y14_N4; Fanout = 1; REG Node = 'tingche:inst1\|q\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { tingche:inst1|Mux6~38 tingche:inst1|q[1] } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.768 ns ( 33.97 % ) " "Info: Total cell delay = 1.768 ns ( 33.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.436 ns ( 66.03 % ) " "Info: Total interconnect delay = 3.436 ns ( 66.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { tingche:inst1|l_num[2] tingche:inst1|tmp~18034 tingche:inst1|tmp~18081 tingche:inst1|Mux6~37 tingche:inst1|Mux6~38 tingche:inst1|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.204 ns" { tingche:inst1|l_num[2] {} tingche:inst1|tmp~18034 {} tingche:inst1|tmp~18081 {} tingche:inst1|Mux6~37 {} tingche:inst1|Mux6~38 {} tingche:inst1|q[1] {} } { 0.000ns 0.590ns 1.274ns 0.438ns 0.696ns 0.438ns } { 0.000ns 0.442ns 0.442ns 0.292ns 0.114ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.029 ns - Smallest " "Info: - Smallest clock skew is 0.029 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 90 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 90; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 -32 136 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns tingche:inst1\|q\[1\] 2 REG LC_X9_Y14_N4 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X9_Y14_N4; Fanout = 1; REG Node = 'tingche:inst1\|q\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk tingche:inst1|q[1] } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk tingche:inst1|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} tingche:inst1|q[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.925 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 90 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 90; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 -32 136 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns tingche:inst1\|l_num\[2\] 2 REG LC_X11_Y12_N4 16 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y12_N4; Fanout = 16; REG Node = 'tingche:inst1\|l_num\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { clk tingche:inst1|l_num[2] } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { clk tingche:inst1|l_num[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { clk {} clk~out0 {} tingche:inst1|l_num[2] {} } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk tingche:inst1|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} tingche:inst1|q[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { clk tingche:inst1|l_num[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { clk {} clk~out0 {} tingche:inst1|l_num[2] {} } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { tingche:inst1|l_num[2] tingche:inst1|tmp~18034 tingche:inst1|tmp~18081 tingche:inst1|Mux6~37 tingche:inst1|Mux6~38 tingche:inst1|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.204 ns" { tingche:inst1|l_num[2] {} tingche:inst1|tmp~18034 {} tingche:inst1|tmp~18081 {} tingche:inst1|Mux6~37 {} tingche:inst1|Mux6~38 {} tingche:inst1|q[1] {} } { 0.000ns 0.590ns 1.274ns 0.438ns 0.696ns 0.438ns } { 0.000ns 0.442ns 0.442ns 0.292ns 0.114ns 0.478ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk tingche:inst1|q[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} tingche:inst1|q[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { clk tingche:inst1|l_num[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { clk {} clk~out0 {} tingche:inst1|l_num[2] {} } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}