tingchechang.fit.qmsg

停车场显示是日常生活中使用很平常的系统

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.551 ns register register " "Info: Estimated most critical path is register to register delay of 4.551 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tingche:inst1\|l_num\[1\] 1 REG LAB_X11_Y10 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y10; Fanout = 16; REG Node = 'tingche:inst1\|l_num\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { tingche:inst1|l_num[1] } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.114 ns) 0.782 ns tingche:inst1\|tmp~18042 2 COMB LAB_X11_Y10 14 " "Info: 2: + IC(0.668 ns) + CELL(0.114 ns) = 0.782 ns; Loc. = LAB_X11_Y10; Fanout = 14; COMB Node = 'tingche:inst1\|tmp~18042'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.782 ns" { tingche:inst1|l_num[1] tingche:inst1|tmp~18042 } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.964 ns) + CELL(0.442 ns) 2.188 ns tingche:inst1\|tmp~18069 3 COMB LAB_X10_Y8 1 " "Info: 3: + IC(0.964 ns) + CELL(0.442 ns) = 2.188 ns; Loc. = LAB_X10_Y8; Fanout = 1; COMB Node = 'tingche:inst1\|tmp~18069'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.406 ns" { tingche:inst1|tmp~18042 tingche:inst1|tmp~18069 } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 2.841 ns tingche:inst1\|Mux4~39 4 COMB LAB_X10_Y8 1 " "Info: 4: + IC(0.211 ns) + CELL(0.442 ns) = 2.841 ns; Loc. = LAB_X10_Y8; Fanout = 1; COMB Node = 'tingche:inst1\|Mux4~39'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { tingche:inst1|tmp~18069 tingche:inst1|Mux4~39 } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.292 ns) 3.733 ns tingche:inst1\|Mux4~40 5 COMB LAB_X9_Y8 1 " "Info: 5: + IC(0.600 ns) + CELL(0.292 ns) = 3.733 ns; Loc. = LAB_X9_Y8; Fanout = 1; COMB Node = 'tingche:inst1\|Mux4~40'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.892 ns" { tingche:inst1|Mux4~39 tingche:inst1|Mux4~40 } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.607 ns) 4.551 ns tingche:inst1\|q\[3\] 6 REG LAB_X9_Y8 1 " "Info: 6: + IC(0.211 ns) + CELL(0.607 ns) = 4.551 ns; Loc. = LAB_X9_Y8; Fanout = 1; REG Node = 'tingche:inst1\|q\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.818 ns" { tingche:inst1|Mux4~40 tingche:inst1|q[3] } "NODE_NAME" } } { "tingche.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/tingche.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.897 ns ( 41.68 % ) " "Info: Total cell delay = 1.897 ns ( 41.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.654 ns ( 58.32 % ) " "Info: Total interconnect delay = 2.654 ns ( 58.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.551 ns" { tingche:inst1|l_num[1] tingche:inst1|tmp~18042 tingche:inst1|tmp~18069 tingche:inst1|Mux4~39 tingche:inst1|Mux4~40 tingche:inst1|q[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X0_Y0 X11_Y10 " "Info: Peak interconnect usage is 4% of the available device resources in the region that extends from location X0_Y0 to location X11_Y10" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "8 " "Warning: Following 8 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ledmg\[7\] GND " "Info: Pin ledmg\[7\] has GND driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ledmg[7] } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ledmg\[7\]" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 800 976 32 "ledmg\[7..0\]" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledmg[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ledmg\[6\] GND " "Info: Pin ledmg\[6\] has GND driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ledmg[6] } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ledmg\[6\]" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 800 976 32 "ledmg\[7..0\]" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledmg[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ledmg\[5\] GND " "Info: Pin ledmg\[5\] has GND driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ledmg[5] } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ledmg\[5\]" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 800 976 32 "ledmg\[7..0\]" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledmg[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ledmg\[4\] GND " "Info: Pin ledmg\[4\] has GND driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ledmg[4] } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ledmg\[4\]" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 800 976 32 "ledmg\[7..0\]" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledmg[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ledmg\[3\] GND " "Info: Pin ledmg\[3\] has GND driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ledmg[3] } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ledmg\[3\]" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 800 976 32 "ledmg\[7..0\]" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledmg[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ledmg\[2\] GND " "Info: Pin ledmg\[2\] has GND driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ledmg[2] } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ledmg\[2\]" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 800 976 32 "ledmg\[7..0\]" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledmg[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ledmg\[1\] GND " "Info: Pin ledmg\[1\] has GND driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ledmg[1] } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ledmg\[1\]" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 800 976 32 "ledmg\[7..0\]" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledmg[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ledmg\[0\] GND " "Info: Pin ledmg\[0\] has GND driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ledmg[0] } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ledmg\[0\]" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 800 976 32 "ledmg\[7..0\]" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledmg[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/stu/桌面/ting2/tingchechang.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/stu/桌面/ting2/tingchechang.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "190 " "Info: Peak virtual memory: 190 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 30 21:11:10 2002 " "Info: Processing ended: Mon Sep 30 21:11:10 2002" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Info: Total CPU time (on all processors): 00:00:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}