prev_cmp_tingchechang.fit.qmsg

停车场显示是日常生活中使用很平常的系统

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 30 21:06:27 2002 " "Info: Processing started: Mon Sep 30 21:06:27 2002" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off tingchechang -c tingchechang " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off tingchechang -c tingchechang" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "tingchechang EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"tingchechang\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 0 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 24 " "Info: Pin ~nCSO~ is reserved at location 24" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 37 " "Info: Pin ~ASDO~ is reserved at location 37" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 152 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 152" {  } { { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 16 -32 136 32 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "hello Global clock " "Info: Automatically promoted some destinations of signal \"hello\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "HELLO:inst\|process3~0 " "Info: Destination \"HELLO:inst\|process3~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|ledmr\[6\]~1463 " "Info: Destination \"jieguo:inst5\|ledmr\[6\]~1463\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|ledmr\[5\]~1464 " "Info: Destination \"jieguo:inst5\|ledmr\[5\]~1464\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|ledmr\[3\]~1466 " "Info: Destination \"jieguo:inst5\|ledmr\[3\]~1466\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|ledmr\[2\]~1467 " "Info: Destination \"jieguo:inst5\|ledmr\[2\]~1467\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|ledmr\[1\]~1468 " "Info: Destination \"jieguo:inst5\|ledmr\[1\]~1468\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|ledmr\[0\]~1469 " "Info: Destination \"jieguo:inst5\|ledmr\[0\]~1469\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 21 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|shumaguan\[4\]~2930 " "Info: Destination \"jieguo:inst5\|shumaguan\[4\]~2930\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|shumaguan\[2\]~2941 " "Info: Destination \"jieguo:inst5\|shumaguan\[2\]~2941\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "jieguo:inst5\|shumaguan\[1\]~2947 " "Info: Destination \"jieguo:inst5\|shumaguan\[1\]~2947\" may be non-global or may not use global clock" {  } { { "jieguo.vhd" "" { Text "C:/Documents and Settings/stu/桌面/ting2/jieguo.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0 "" 0 0}  } { { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 48 -32 136 64 "hello" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "hello " "Info: Pin \"hello\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { hello } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "hello" } } } } { "tingchechang.bdf" "" { Schematic "C:/Documents and Settings/stu/桌面/ting2/tingchechang.bdf" { { 48 -32 136 64 "hello" "" } } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { hello } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0 0}