fenpin.vhd

来自「停车场显示是日常生活中使用很平常的系统」· VHDL 代码 · 共 23 行

--为了显示效果更佳，将时钟适当分频；此模块可不用
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity fenpin is
	port(
		clk:in std_logic;
		fenpin:out std_logic
		);
end fenpin;
architecture fenpin of fenpin is
signal clk1:std_logic_vector(3 downto 0);
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			clk1<=clk1+1;
		end if;
		fenpin<=clk;
	end process;
end fenpin;