📄 ppcopc.cc
字号:
{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },{ "vnot", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VAB } },{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vmr", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VAB } },{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },{ "vsldoi128", VX128_5(4, 16), VX128_5_MASK, PPCVEC, { VS128, VA128, VB128, SHB } },{ "lvsl128", VX128_1(4, 3), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "lvsr128", VX128_1(4, 67), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "lvewx128", VX128_1(4, 131), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "lvx128", VX128_1(4, 195), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "stvewx128", VX128_1(4, 387), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "stvx128", VX128_1(4, 451), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "lvxl128", VX128_1(4, 707), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "stvxl128", VX128_1(4, 963), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "lvlx128", VX128_1(4, 1027), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "lvrx128", VX128_1(4, 1091), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "stvlx128", VX128_1(4, 1283), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "stvrx128", VX128_1(4, 1347), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "lvlxl128", VX128_1(4, 1539), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "lvrxl128", VX128_1(4, 1603), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "stvlxl128", VX128_1(4, 1795), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "stvrxl128", VX128_1(4, 1859), VX128_1_MASK, PPCVEC, { VS128, RA0, RB } },{ "vperm128", VX128_2(5, 0), VX128_2_MASK, PPCVEC, { VD128, VA128, VB128, VC128 } },{ "vaddfp128", VX128(5, 16), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vsubfp128", VX128(5, 80), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vmulfp128", VX128(5, 144), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vmaddfp128", VX128(5, 208), VX128_MASK, PPCVEC, { VD128, VA128, VB128, VS128 } },{ "vmaddcfp128",VX128(5, 272), VX128_MASK, PPCVEC, { VD128, VA128, VS128, VB128 } },{ "vnmsubfp128",VX128(5, 336), VX128_MASK, PPCVEC, { VD128, VA128, VB128, VS128 } },{ "vmsum3fp128",VX128(5, 400), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vmsum4fp128",VX128(5, 464), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vpkshss128", VX128(5, 512), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vand128", VX128(5, 528), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vpkshus128", VX128(5, 576), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vandc128", VX128(5, 592), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vpkswss128", VX128(5, 640), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vnor128", VX128(5, 656), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vpkswus128", VX128(5, 704), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vor128", VX128(5, 720), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vpkuhum128", VX128(5, 768), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vxor128", VX128(5, 784), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vpkuhus128", VX128(5, 832), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vsel128", VX128(5, 848), VX128_MASK, PPCVEC, { VD128, VA128, VB128, VS128 } },{ "vpkuwum128", VX128(5, 896), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vslo128", VX128(5, 912), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vpkuwus128", VX128(5, 960), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vsro128", VX128(5, 976), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vpermwi128", VX128_P(6, 528), VX128_P_MASK, PPCVEC, { VD128, VB128, VPERM128 } },{ "vcfpsxws128", VX128_3(6, 560), VX128_3_MASK, PPCVEC, { VD128, VB128, SIMM } },{ "vcfpuxws128", VX128_3(6, 624), VX128_3_MASK, PPCVEC, { VD128, VB128, UIMM } },{ "vcsxwfp128", VX128_3(6, 688), VX128_3_MASK, PPCVEC, { VD128, VB128, SIMM } },{ "vcuxwfp128", VX128_3(6, 752), VX128_3_MASK, PPCVEC, { VD128, VB128, UIMM } },{ "vrfim128", VX128_3(6, 816), VX128_3_MASK, PPCVEC, { VD128, VB128 } },{ "vrfin128", VX128_3(6, 880), VX128_3_MASK, PPCVEC, { VD128, VB128 } },{ "vrfip128", VX128_3(6, 944), VX128_3_MASK, PPCVEC, { VD128, VB128 } },{ "vrfiz128", VX128_3(6, 1008), VX128_3_MASK, PPCVEC, { VD128, VB128 } },{ "vpkd3d128", VX128_4(6, 1552), VX128_4_MASK, PPCVEC, { VD128, VB128, VD3D0, VD3D1, VD3D2} },{ "vrefp128", VX128_3(6, 1584), VX128_3_MASK, PPCVEC, { VD128, VB128 } },{ "vrsqrtefp128",VX128_3(6, 1648), VX128_3_MASK, PPCVEC, { VD128, VB128 } },{ "vexptefp128", VX128_3(6, 1712), VX128_3_MASK, PPCVEC, { VD128, VB128 } },{ "vlogefp128", VX128_3(6, 1776), VX128_3_MASK, PPCVEC, { VD128, VB128 } },{ "vrlimi128", VX128_4(6, 1808), VX128_4_MASK, PPCVEC, { VD128, VB128, UIMM, VD3D2} },{ "vspltw128", VX128_3(6, 1840), VX128_3_MASK, PPCVEC, { VD128, VB128, UIMM } },{ "vspltisw128", VX128_3(6, 1904), VX128_3_MASK, PPCVEC, { VD128, VB128, SIMM } },{ "vupkd3d128", VX128_3(6, 2032), VX128_3_MASK, PPCVEC, { VD128, VB128, UIMM } },{ "vcmpeqfp128", VX128(6, 0), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpeqfp128.",VX128(6, 64), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vrlw128", VX128(6, 80), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpgefp128", VX128(6, 128), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpgefp128.",VX128(6, 192), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vslw128", VX128(6, 208), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpgtfp128", VX128(6, 256), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpgtfp128.",VX128(6, 320), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vsraw128", VX128(6, 336), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpbfp128", VX128(6, 384), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpbfp128.", VX128(6, 448), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vsrw128", VX128(6, 464), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpequw128", VX128(6, 512), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vcmpequw128.",VX128(6, 576), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vmaxfp128", VX128(6, 640), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vminfp128", VX128(6, 704), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vmrghw128", VX128(6, 768), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vmrglw128", VX128(6, 832), VX128_MASK, PPCVEC, { VD128, VA128, VB128 } },{ "vupkhsb128", VX128(6, 896), VX128_MASK, PPCVEC, { VD128, VB128 } },{ "vupklsb128", VX128(6, 960), VX128_MASK, PPCVEC, { VD128, VB128 } },{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },{ "addis", OP(15), OP_MASK, PPCCOM, { RT, RA0, SISIGNOPT } },{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },{ "bgela-", BBOCB(16,BOF,CBLT,⌨️ 快捷键说明
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