ia64opc.h

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	IA64_OPCODE_FOR_F1_F2_F3,
	IA64_OPCODE_FXOR_F1_F2_F3,
	IA64_OPCODE_FPMERGE_S_F1_F2_F3,
	IA64_OPCODE_FPMERGE_NS_F1_F2_F3,
	IA64_OPCODE_FPMERGE_SE_F1_F2_F3,
	IA64_OPCODE_FCVT_FX_S0_F1_F2,
	IA64_OPCODE_FCVT_FX_S1_F1_F2,
	IA64_OPCODE_FCVT_FX_S2_F1_F2,
	IA64_OPCODE_FCVT_FX_S3_F1_F2,
	IA64_OPCODE_FCVT_FXU_S0_F1_F2,
	IA64_OPCODE_FCVT_FXU_S1_F1_F2,
	IA64_OPCODE_FCVT_FXU_S2_F1_F2,
	IA64_OPCODE_FCVT_FXU_S3_F1_F2,
	IA64_OPCODE_FCVT_FX_TRUNC_S0_F1_F2,
	IA64_OPCODE_FCVT_FX_TRUNC_S1_F1_F2,
	IA64_OPCODE_FCVT_FX_TRUNC_S2_F1_F2,
	IA64_OPCODE_FCVT_FX_TRUNC_S3_F1_F2,
	IA64_OPCODE_FCVT_FXU_TRUNC_S0_F1_F2,
	IA64_OPCODE_FCVT_FXU_TRUNC_S1_F1_F2,
	IA64_OPCODE_FCVT_FXU_TRUNC_S2_F1_F2,
	IA64_OPCODE_FCVT_FXU_TRUNC_S3_F1_F2,
	IA64_OPCODE_FPCVT_FX_S0_F1_F2,
	IA64_OPCODE_FPCVT_FX_S1_F1_F2,
	IA64_OPCODE_FPCVT_FX_S2_F1_F2,
	IA64_OPCODE_FPCVT_FX_S3_F1_F2,
	IA64_OPCODE_FPCVT_FXU_S0_F1_F2,
	IA64_OPCODE_FPCVT_FXU_S1_F1_F2,
	IA64_OPCODE_FPCVT_FXU_S2_F1_F2,
	IA64_OPCODE_FPCVT_FXU_S3_F1_F2,
	IA64_OPCODE_FPCVT_FX_TRUNC_S0_F1_F2,
	IA64_OPCODE_FPCVT_FX_TRUNC_S1_F1_F2,
	IA64_OPCODE_FPCVT_FX_TRUNC_S2_F1_F2,
	IA64_OPCODE_FPCVT_FX_TRUNC_S3_F1_F2,
	IA64_OPCODE_FPCVT_FXU_TRUNC_S0_F1_F2,
	IA64_OPCODE_FPCVT_FXU_TRUNC_S1_F1_F2,
	IA64_OPCODE_FPCVT_FXU_TRUNC_S2_F1_F2,
	IA64_OPCODE_FPCVT_FXU_TRUNC_S3_F1_F2,
	IA64_OPCODE_FCVT_XF_F1_F2,
	IA64_OPCODE_FSETC_S0_AMASK7_OMASK7,
	IA64_OPCODE_FSETC_S1_AMASK7_OMASK7,
	IA64_OPCODE_FSETC_S2_AMASK7_OMASK7,
	IA64_OPCODE_FSETC_S3_AMASK7_OMASK7,
	IA64_OPCODE_FCLRF_S0,
	IA64_OPCODE_FCLRF_S1,
	IA64_OPCODE_FCLRF_S2,
	IA64_OPCODE_FCLRF_S3,
	IA64_OPCODE_FCHKF_S0_TARGET25,
	IA64_OPCODE_FCHKF_S1_TARGET25,
	IA64_OPCODE_FCHKF_S2_TARGET25,
	IA64_OPCODE_FCHKF_S3_TARGET25,
	IA64_OPCODE_BREAK_F_IMM21,
	IA64_OPCODE_NOP_F_IMM21,
	IA64_OPCODE_BREAK_X_IMM62,
	IA64_OPCODE_NOP_X_IMM62,
	IA64_OPCODE_MOVL_R1_IMM64,
	IA64_OPCODE_BRL_COND_SPTK_FEW_TARGET64,
	IA64_OPCODE_BRL_COND_SPTK_MANY_TARGET64,
	IA64_OPCODE_BRL_COND_SPNT_FEW_TARGET64,
	IA64_OPCODE_BRL_COND_SPNT_MANY_TARGET64,
	IA64_OPCODE_BRL_COND_DPTK_FEW_TARGET64,
	IA64_OPCODE_BRL_COND_DPTK_MANY_TARGET64,
	IA64_OPCODE_BRL_COND_DPNT_FEW_TARGET64,
	IA64_OPCODE_BRL_COND_DPNT_MANY_TARGET64,
	IA64_OPCODE_BRL_COND_SPTK_FEW_CLR_TARGET64,
	IA64_OPCODE_BRL_COND_SPTK_MANY_CLR_TARGET64,
	IA64_OPCODE_BRL_COND_SPNT_FEW_CLR_TARGET64,
	IA64_OPCODE_BRL_COND_SPNT_MANY_CLR_TARGET64,
	IA64_OPCODE_BRL_COND_DPTK_FEW_CLR_TARGET64,
	IA64_OPCODE_BRL_COND_DPTK_MANY_CLR_TARGET64,
	IA64_OPCODE_BRL_COND_DPNT_FEW_CLR_TARGET64,
	IA64_OPCODE_BRL_COND_DPNT_MANY_CLR_TARGET64,
	IA64_OPCODE_BRL_CALL_SPTK_FEW_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_SPTK_MANY_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_SPNT_FEW_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_SPNT_MANY_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_DPTK_FEW_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_DPTK_MANY_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_DPNT_FEW_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_DPNT_MANY_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_SPTK_FEW_CLR_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_SPTK_MANY_CLR_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_SPNT_FEW_CLR_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_SPNT_MANY_CLR_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_DPTK_FEW_CLR_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_DPTK_MANY_CLR_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_DPNT_FEW_CLR_B1_TARGET64,
	IA64_OPCODE_BRL_CALL_DPNT_MANY_CLR_B1_TARGET64,
	IA64_OPCODE_INST_LAST
};

enum IA64EnumOperandRole {
    IA64_OPROLE_NONE = 0,
    IA64_OPROLE_SRC,
    IA64_OPROLE_DST,
    IA64_OPROLE_SRC_DST,
    IA64_OPROLE_DST_SRC,
    OPROLE_LAST
};

enum IA64EnumOperandType {
IA64_OPTYPE_NONE = 0,
IA64_OPTYPE_REG_FIRST,      /* The following types are registers */
IA64_OPTYPE_IREG,           /* Integer register */
IA64_OPTYPE_IREG_R0_3,      /* r0-r3 */
IA64_OPTYPE_IREG_R0,        /* Integer register R0 */
IA64_OPTYPE_IREG_R1_127,    /* r1-r127 */
IA64_OPTYPE_FREG,           /* FP register */
IA64_OPTYPE_FREG_F2_127,    /* f2-f127 */
IA64_OPTYPE_BR,             /* branch register */
IA64_OPTYPE_IP,             /* instruction pointer, not encoded */
IA64_OPTYPE_PREG,           /* predicate */
IA64_OPTYPE_PREGS_ALL,      /* the predicate register */
IA64_OPTYPE_PREGS_ROT,      /* rotating predicates */
IA64_OPTYPE_APP_REG_GRP_LOW,         /* application registers 0-63*/
IA64_OPTYPE_APP_REG_GRP_HIGH,        /* application registers 64-127*/
IA64_OPTYPE_APP_CCV,        /* ar.ccv */
IA64_OPTYPE_APP_PFS,        /* ar.pfs */
IA64_OPTYPE_CR,             /* control registers */
IA64_OPTYPE_PSR_L,          /* psr.l */
IA64_OPTYPE_PSR_UM,         /* psr.um */
IA64_OPTYPE_FPSR,           /* decoder operand types */
IA64_OPTYPE_CFM,
IA64_OPTYPE_PSR,
IA64_OPTYPE_IFM,
IA64_OPTYPE_REG_LAST,       /* End of register - types */
IA64_OPTYPE_REGFILE_FIRST,  /* The following types are register-files */
IA64_OPTYPE_PMC,
IA64_OPTYPE_PMD,
IA64_OPTYPE_PKR,
IA64_OPTYPE_RR,
IA64_OPTYPE_IBR,
IA64_OPTYPE_DBR,
IA64_OPTYPE_ITR,
IA64_OPTYPE_DTR,
IA64_OPTYPE_MSR,
IA64_OPTYPE_CPUID,
IA64_OPTYPE_REGFILE_LAST,   /* End of register-file types */
IA64_OPTYPE_IMM_FIRST,      /* The following types are immediates */
IA64_OPTYPE_UIMM,           /* unsigned immediate */
IA64_OPTYPE_SIMM,           /* signed immediate */
IA64_OPTYPE_IREG_NUM,       /* ireg in syntax and imm7 in encodings */
IA64_OPTYPE_FREG_NUM,       /* freg in syntax and imm7 in encodings */
IA64_OPTYPE_SSHIFT_REL,     /* pc relative signed immediate
					    which is shifted by 4 */
IA64_OPTYPE_SSHIFT_1,       /* unsigned immediate which has to be
					    shifted 1 bit */
IA64_OPTYPE_SSHIFT_16,      /* unsigned immediate which has to be
					    shifted 16 bits */
IA64_OPTYPE_COUNT_123,      /* immediate which can have the values of
					    1, 2, 3 only */
IA64_OPTYPE_COUNT_PACK,     /* immediate which can have the values of
							 0, 7, 15, 16 only */
IA64_OPTYPE_UDEC,           /* unsigned immediate which has to be
					    decremented by 1 by the assembler */
IA64_OPTYPE_SDEC,           /* signed immediate which has to be
					    decremented by 1 by the assembler */
IA64_OPTYPE_CCOUNT,         /* in pshl[24] - uimm5 in syntax, but encoded
					    as its 2's complement */
IA64_OPTYPE_CPOS,           /* in dep fixed form - uimm6 in syntax, but encoded
					    as its 2's complement */
IA64_OPTYPE_SEMAPHORE_INC,  /* immediate which is a semaphore increment amount
					    can have the values of -16,-8,-4,-1,
					    1,4,8,16 */
IA64_OPTYPE_ONE,            /* the number 1 */
IA64_OPTYPE_FCLASS,         /* immediate of the fclass instruction */
IA64_OPTYPE_CMP_UIMM,       /* unsigned immediate of cmp geu and ltu */
IA64_OPTYPE_CMP_UIMM_DEC,   /* unsigned immediate of cmp gtu and leu */
IA64_OPTYPE_CMP4_UIMM,      /* unsigned immediate of cmp4 geu and ltu */
IA64_OPTYPE_CMP4_UIMM_DEC,  /* unsigned immediate of cmp4 gtu and leu */
IA64_OPTYPE_ALLOC_IOL,      /* for alloc : input, local, and output
					    can be 0-96 */
IA64_OPTYPE_ALLOC_ROT,      /* for alloc : rotating, can be 0-96 */
IA64_OPTYPE_MUX1,           /* immediate of the mux1 instruction */
IA64_OPTYPE_EIGHT,          /* immediate for ldfps base update form can have value 8 */
IA64_OPTYPE_SIXTEEN,        /* immediate for ldfp8 and ldfpd base update form can have value 16 */
IA64_OPTYPE_IMM_LAST,       /* End of immediate types */
IA64_OPTYPE_MEM,            /* memory address */
IA64_OPTYPE_LAST
};

enum IA64EnumOpcodeFormat {
	 IA64_FORMAT_NONE = 0,
	 IA64_FORMAT_A1,
	 IA64_FORMAT_A2,
	 IA64_FORMAT_A3,
	 IA64_FORMAT_A4,
	 IA64_FORMAT_A4_1,
	 IA64_FORMAT_A5,
	 IA64_FORMAT_A6,
	 IA64_FORMAT_A6_1,
	 IA64_FORMAT_A6_2,
	 IA64_FORMAT_A6_3,
	 IA64_FORMAT_A6_4,
	 IA64_FORMAT_A6_5,
	 IA64_FORMAT_A6_6,
	 IA64_FORMAT_A6_7,
	 IA64_FORMAT_A7,
	 IA64_FORMAT_A7_1,
	 IA64_FORMAT_A7_2,
	 IA64_FORMAT_A7_3,
	 IA64_FORMAT_A7_4,
	 IA64_FORMAT_A7_5,
	 IA64_FORMAT_A7_6,
	 IA64_FORMAT_A7_7,
	 IA64_FORMAT_A8,
	 IA64_FORMAT_A8_1,
	 IA64_FORMAT_A8_2,
	 IA64_FORMAT_A8_3,
	 IA64_FORMAT_A9,
	 IA64_FORMAT_A10,
	 IA64_FORMAT_I1,
	 IA64_FORMAT_I2,
	 IA64_FORMAT_I3,
	 IA64_FORMAT_I4,
	 IA64_FORMAT_I5,
	 IA64_FORMAT_I6,
	 IA64_FORMAT_I7,
	 IA64_FORMAT_I8,
	 IA64_FORMAT_I9,
	 IA64_FORMAT_I10,
	 IA64_FORMAT_I11,
	 IA64_FORMAT_I12,
	 IA64_FORMAT_I13,
	 IA64_FORMAT_I14,
	 IA64_FORMAT_I15,
	 IA64_FORMAT_I16,
	 IA64_FORMAT_I16_1,
	 IA64_FORMAT_I16_2,
	 IA64_FORMAT_I16_3,
	 IA64_FORMAT_I17,
	 IA64_FORMAT_I17_1,
	 IA64_FORMAT_I17_2,
	 IA64_FORMAT_I17_3,
	 IA64_FORMAT_I19,
	 IA64_FORMAT_I20,
	 IA64_FORMAT_I21,
	 IA64_FORMAT_I22,
	 IA64_FORMAT_I23,
	 IA64_FORMAT_I24,
	 IA64_FORMAT_I25,
	 IA64_FORMAT_I26,
	 IA64_FORMAT_I27,
	 IA64_FORMAT_I28,
	 IA64_FORMAT_I29,
	 IA64_FORMAT_M1,
	 IA64_FORMAT_M2,
	 IA64_FORMAT_M3,
	 IA64_FORMAT_M4,
	 IA64_FORMAT_M5,
	 IA64_FORMAT_M6,
	 IA64_FORMAT_M7,
	 IA64_FORMAT_M8,
	 IA64_FORMAT_M9,
	 IA64_FORMAT_M10,
	 IA64_FORMAT_M11,
	 IA64_FORMAT_M12,
	 IA64_FORMAT_M13,
	 IA64_FORMAT_M14,
	 IA64_FORMAT_M15,
	 IA64_FORMAT_M16,
	 IA64_FORMAT_M17,
	 IA64_FORMAT_M18,
	 IA64_FORMAT_M19,
	 IA64_FORMAT_M20,
	 IA64_FORMAT_M21,
	 IA64_FORMAT_M22,
	 IA64_FORMAT_M23,
	 IA64_FORMAT_M24,
	 IA64_FORMAT_M25,
	 IA64_FORMAT_M26,
	 IA64_FORMAT_M27,
	 IA64_FORMAT_M28,
	 IA64_FORMAT_M29,
	 IA64_FORMAT_M30,
	 IA64_FORMAT_M31,
	 IA64_FORMAT_M32,
	 IA64_FORMAT_M33,
	 IA64_FORMAT_M34,
	 IA64_FORMAT_M34_1,
	 IA64_FORMAT_M35,
	 IA64_FORMAT_M36,
	 IA64_FORMAT_M37,
	 IA64_FORMAT_M38,
	 IA64_FORMAT_M39,
	 IA64_FORMAT_M40,
	 IA64_FORMAT_M41,
	 IA64_FORMAT_M42,
	 IA64_FORMAT_M43,
	 IA64_FORMAT_M44,
	 IA64_FORMAT_M45,
	 IA64_FORMAT_M46,
	 IA64_FORMAT_M1001,
	 IA64_FORMAT_B1,
	 IA64_FORMAT_B2,
	 IA64_FORMAT_B3,
	 IA64_FORMAT_B4,
	 IA64_FORMAT_B5,
	 IA64_FORMAT_B6,
	 IA64_FORMAT_B7,
	 IA64_FORMAT_B8,
	 IA64_FORMAT_B9,
	 IA64_FORMAT_F1,
	 IA64_FORMAT_F1_1,
	 IA64_FORMAT_F2,
	 IA64_FORMAT_F3,
	 IA64_FORMAT_F4,
	 IA64_FORMAT_F4_1,
	 IA64_FORMAT_F4_2,
	 IA64_FORMAT_F4_3,
	 IA64_FORMAT_F4_4,
	 IA64_FORMAT_F4_5,
	 IA64_FORMAT_F4_6,
	 IA64_FORMAT_F4_7,
	 IA64_FORMAT_F5,
	 IA64_FORMAT_F5_1,
	 IA64_FORMAT_F5_2,
	 IA64_FORMAT_F5_3,
	 IA64_FORMAT_F6,
	 IA64_FORMAT_F7,
	 IA64_FORMAT_F8,
	 IA64_FORMAT_F8_4,
	 IA64_FORMAT_F9,
	 IA64_FORMAT_F9_1,
	 IA64_FORMAT_F10,
	 IA64_FORMAT_F11,
	 IA64_FORMAT_F12,
	 IA64_FORMAT_F13,
	 IA64_FORMAT_F14,
	 IA64_FORMAT_F15,
	 IA64_FORMAT_X1,
	 IA64_FORMAT_X2,
	 IA64_FORMAT_X3,
	 IA64_FORMAT_X4,
	 IA64_FORMAT_X41,
	 IA64_FORMAT_LAST
};

enum IA64EnumOpcodeTemplateRole {
    IA64_TROLE_NONE = 0,
    IA64_TROLE_ALU,
    IA64_TROLE_BR,
    IA64_TROLE_FP,
    IA64_TROLE_INT,
    IA64_TROLE_LONG,
    IA64_TROLE_MEM,
    IA64_TROLE_MIBF,
    IA64_TROLE_LAST
};

#define IA64_DECISION_TREE_LEAF_NODE(node) ((byte)((node).pos) == 0xff)

struct IA64Template {
	byte stop;
	byte slot[3];
};

struct IA64DecisionTreeEntry {
	uint16 next_node;
	char pos;
	char size;
};

struct IA64Operand {
	IA64EnumOperandRole role;
	IA64EnumOperandType type;
};

struct IA64OpcodeEntry {
	const char			*name;
	IA64EnumOpcodeFormat		format;
	IA64EnumOpcodeTemplateRole   	role;
	IA64Operand			op1; // FIXME make array
	IA64Operand			op2;
	IA64Operand			op3;
	IA64Operand			op4;
	IA64Operand			op5;
	IA64Operand			op6;
};
																						  
extern IA64Template IA64Templates[];
extern IA64DecisionTreeEntry IA64DecisionTree[];
extern IA64OpcodeEntry IA64OpcodeTable[];


#endif