📄 mc56f835x.h
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#define FCMB7_CONTROL ( FC_BASE + 0x78 ) //Message Buffer 7 Control / Status Register
#define FCMB7_ID_HIGH ( FC_BASE + 0x79 ) //Message Buffer 7 ID High Register
#define FCMB7_ID_LOW ( FC_BASE + 0x7A ) //Message Buffer 7 ID Low Register
#define FCMB7_DATA ( FC_BASE + 0x7B ) //Message Buffer 7 Data Register
#define FCMB8_CONTROL ( FC_BASE + 0x80 ) //Message Buffer 8 Control / Status Register
#define FCMB8_ID_HIGH ( FC_BASE + 0x81 ) //Message Buffer 8 ID High Register
#define FCMB8_ID_LOW ( FC_BASE + 0x82 ) //Message Buffer 8 ID Low Register
#define FCMB8_DATA ( FC_BASE + 0x83 ) //Message Buffer 8 Data Register
#define FCMB9_CONTROL ( FC_BASE + 0x88 ) //Message Buffer 9 Control / Status Register
#define FCMB9_ID_HIGH ( FC_BASE + 0x89 ) //Message Buffer 9 ID High Register
#define FCMB9_ID_LOW ( FC_BASE + 0x8A ) //Message Buffer 9 ID Low Register
#define FCMB9_DATA ( FC_BASE + 0x8B ) //Message Buffer 9 Data Register
#define FCMB10_CONTROL ( FC_BASE + 0x90 ) //Message Buffer 10 Control / Status Register
#define FCMB10_ID_HIGH ( FC_BASE + 0x91 ) //Message Buffer 10 ID High Register
#define FCMB10_ID_LOW ( FC_BASE + 0x92 ) //Message Buffer 10 ID Low Register
#define FCMB10_DATA ( FC_BASE + 0x93 ) //Message Buffer 10 Data Register
#define FCMB11_CONTROL ( FC_BASE + 0x98 ) //Message Buffer 11 Control / Status Register
#define FCMB11_ID_HIGH ( FC_BASE + 0x99 ) //Message Buffer 11 ID High Register
#define FCMB11_ID_LOW ( FC_BASE + 0x9A ) //Message Buffer 11 ID Low Register
#define FCMB11_DATA ( FC_BASE + 0x9B ) //Message Buffer 11 Data Register
#define FCMB12_CONTROL ( FC_BASE + 0xA0 ) //Message Buffer 12 Control / Status Register
#define FCMB12_ID_HIGH ( FC_BASE + 0xA1 ) //Message Buffer 12 ID High Register
#define FCMB12_ID_LOW ( FC_BASE + 0xA2 ) //Message Buffer 12 ID Low Register
#define FCMB12_DATA ( FC_BASE + 0xA3 ) //Message Buffer 12 Data Register
#define FCMB13_CONTROL ( FC_BASE + 0xA8 ) //Message Buffer 13 Control / Status Register
#define FCMB13_ID_HIGH ( FC_BASE + 0xA9 ) //Message Buffer 13 ID High Register
#define FCMB13_ID_LOW ( FC_BASE + 0xAA ) //Message Buffer 13 ID Low Register
#define FCMB13_DATA ( FC_BASE + 0xAB ) //Message Buffer 13 Data Register
#define FCMB14_CONTROL ( FC_BASE + 0xB0 ) //Message Buffer 14 Control / Status Register
#define FCMB14_ID_HIGH ( FC_BASE + 0xB1 ) //Message Buffer 14 ID High Register
#define FCMB14_ID_LOW ( FC_BASE + 0xB2 ) //Message Buffer 14 ID Low Register
#define FCMB14_DATA ( FC_BASE + 0xB3 ) //Message Buffer 14 Data Register
#define FCMB15_CONTROL ( FC_BASE + 0xB8 ) //Message Buffer 15 Control / Status Register
#define FCMB15_ID_HIGH ( FC_BASE + 0xB9 ) //Message Buffer 15 ID High Register
#define FCMB15_ID_LOW ( FC_BASE + 0xBA ) //Message Buffer 15 ID Low Register
#define FCMB15_DATA ( FC_BASE + 0xBB ) //Message Buffer 15 Data Register
#define Non_Data_Sheet_Format_Version
#ifdef Non_Data_Sheet_Format_Version
// Serial Communications Interface 0 (SCI0)
//#define SCI0_BASE 0x00F280
#define SCI0_DR (SCI0_BASE + 3)
#define SCI0_SR (SCI0_BASE + 2)
#define SCI0_CR (SCI0_BASE + 1)
#define SCI0_BR (SCI0_BASE + 0)
// Serial Communications Interface 1 (SCI1)
//#define SCI1_BASE 0x00F290
#define SCI1_DR (SCI1_BASE + 3)
#define SCI1_SR (SCI1_BASE + 2)
#define SCI1_CR (SCI1_BASE + 1)
#define SCI1_BR (SCI1_BASE + 0)
// Serial Peripheral Interface 0 (SPI0)
//#define SPI0_BASE 0x00F2A0
#define SPI0_DTR (SPI0_BASE + 3)
#define SPI0_DRR (SPI0_BASE + 2)
#define SPI0_DSR (SPI0_BASE + 1)
#define SPI0_SCR (SPI0_BASE + 0)
// Serial Peripheral Interface 1 (SPI1)
//#define SPI1_BASE 0x00F2B0
#define SPI1_DTR (SPI1_BASE + 3)
#define SPI1_DRR (SPI1_BASE + 2)
#define SPI1_DSR (SPI1_BASE + 1)
#define SPI1_SCR (SPI1_BASE + 0)
// Computer Operating Properly (COP)
//#define COP_BASE (0x00F2C0)
#define COPCNTR (COP_BASE + 2)
//#define COPTO (COP_BASE + 1)
//#define COPCTL (COP_BASE + 0)
// Interrupt controller
#define INTC_BASE 0x00F1A0
//#define ICTL (INTC_BASE + 0x1D)
#define TIRQS5 (INTC_BASE + 0x1C)
#define TIRQS4 (INTC_BASE + 0x1B)
#define TIRQS3 (INTC_BASE + 0x1A)
#define TIRQS2 (INTC_BASE + 0x19)
#define TIRQS1 (INTC_BASE + 0x18)
#define TIRQS0 (INTC_BASE + 0x17)
//#define IRQP5 (INTC_BASE + 0x16)
//#define IRQP4 (INTC_BASE + 0x15)
//#define IRQP3 (INTC_BASE + 0x14)
//#define IRQP2 (INTC_BASE + 0x13)
//#define IRQP1 (INTC_BASE + 0x12)
//#define IRQP0 (INTC_BASE + 0x11)
//#define FIVAH1 (INTC_BASE + 0x10)
//#define FIVAL1 (INTC_BASE + 0xF)
//#define FIM1 (INTC_BASE + 0xE)
//#define FIVAH0 (INTC_BASE + 0xD)
//#define FIVAL0 (INTC_BASE + 0xC)
//#define FIM0 (INTC_BASE + 0xB)
//#define VBA (INTC_BASE + 0xA)
//#define IPR9 (INTC_BASE + 0x9)
//#define IPR8 (INTC_BASE + 0x8)
//#define IPR7 (INTC_BASE + 0x7)
//#define IPR6 (INTC_BASE + 0x6)
//#define IPR5 (INTC_BASE + 0x5)
//#define IPR4 (INTC_BASE + 0x4)
//#define IPR3 (INTC_BASE + 0x3)
//#define IPR2 (INTC_BASE + 0x2)
//#define IPR1 (INTC_BASE + 0x1)
//#define IPR0 (INTC_BASE + 0x0)
// System Integration Module (SIM)
//#define SIM_BASE (0x00F350)
//#define SIM_PCE2 (SIM_BASE + 0xF)
//#define SIM_ISALL (SIM_BASE + 0xE)
//#define SIM_ISALH (SIM_BASE + 0xD)
//#define SIM_PCE (SIM_BASE + 0xC)
//#define SIM_GPS (SIM_BASE + 0xB)
//#define SIM_CLKOSR (SIM_BASE + 0xA)
//#define SIM_PUDR (SIM_BASE + 0x8)
//#define SIM_LSH_ID (SIM_BASE + 0x7)
//#define SIM_MSH_ID (SIM_BASE + 0x6)
//#define SIM_SCR3 (SIM_BASE + 0x5)
//#define SIM_SCR2 (SIM_BASE + 0x4)
//#define SIM_SCR1 (SIM_BASE + 0x3)
//#define SIM_SCR0 (SIM_BASE + 0x2)
//#define SIM_RSTSTS (SIM_BASE + 0x1)
//#define SIM_CONTROL (SIM_BASE + 0x0)
// timer
////#define TMRD_BASE 0x00F100
#define TMR_D3_COMSCR (TMRD_BASE + 0x3A)
#define TMR_D3_CMPLD2 (TMRD_BASE + 0x39)
#define TMR_D3_CMPLD1 (TMRD_BASE + 0x38)
#define TMR_D3_SCR (TMRD_BASE + 0x37)
#define TMR_D3_CTRL (TMRD_BASE + 0x36)
#define TMR_D3_CNTR (TMRD_BASE + 0x35)
#define TMR_D3_HOLD (TMRD_BASE + 0x34)
#define TMR_D3_LOAD (TMRD_BASE + 0x33)
#define TMR_D3_CAP (TMRD_BASE + 0x32)
#define TMR_D3_CMP2 (TMRD_BASE + 0x31)
#define TMR_D3_CMP1 (TMRD_BASE + 0x30)
#define TMR_D2_COMSCR (TMRD_BASE + 0x2A)
#define TMR_D2_CMPLD2 (TMRD_BASE + 0x29)
#define TMR_D2_CMPLD1 (TMRD_BASE + 0x28)
#define TMR_D2_SCR (TMRD_BASE + 0x27)
#define TMR_D2_CTRL (TMRD_BASE + 0x26)
#define TMR_D2_CNTR (TMRD_BASE + 0x25)
#define TMR_D2_HOLD (TMRD_BASE + 0x24)
#define TMR_D2_LOAD (TMRD_BASE + 0x23)
#define TMR_D2_CAP (TMRD_BASE + 0x22)
#define TMR_D2_CMP2 (TMRD_BASE + 0x21)
#define TMR_D2_CMP1 (TMRD_BASE + 0x20)
#define TMR_D1_COMSCR (TMRD_BASE + 0x1A)
#define TMR_D1_CMPLD2 (TMRD_BASE + 0x19)
#define TMR_D1_CMPLD1 (TMRD_BASE + 0x18)
#define TMR_D1_SCR (TMRD_BASE + 0x17)
#define TMR_D1_CTRL (TMRD_BASE + 0x16)
#define TMR_D1_CNTR (TMRD_BASE + 0x15)
#define TMR_D1_HOLD (TMRD_BASE + 0x14)
#define TMR_D1_LOAD (TMRD_BASE + 0x13)
#define TMR_D1_CAP (TMRD_BASE + 0x12)
#define TMR_D1_CMP2 (TMRD_BASE + 0x11)
#define TMR_D1_CMP1 (TMRD_BASE + 0x10)
#define TMR_D0_COMSCR (TMRD_BASE + 0xA)
#define TMR_D0_CMPLD2 (TMRD_BASE + 0x9)
#define TMR_D0_CMPLD1 (TMRD_BASE + 0x8)
#define TMR_D0_SCR (TMRD_BASE + 0x7)
#define TMR_D0_CTRL (TMRD_BASE + 0x6)
#define TMR_D0_CNTR (TMRD_BASE + 0x5)
#define TMR_D0_HOLD (TMRD_BASE + 0x4)
#define TMR_D0_LOAD (TMRD_BASE + 0x3)
#define TMR_D0_CAP (TMRD_BASE + 0x2)
#define TMR_D0_CMP2 (TMRD_BASE + 0x1)
#define TMR_D0_CMP1 (TMRD_BASE + 0x0)
//#define TMRC_BASE 0x00F0C0
#define TMR_C3_COMSCR (TMRC_BASE + 0x3A)
#define TMR_C3_CMPLD2 (TMRC_BASE + 0x39)
#define TMR_C3_CMPLD1 (TMRC_BASE + 0x38)
#define TMR_C3_SCR (TMRC_BASE + 0x37)
#define TMR_C3_CTRL (TMRC_BASE + 0x36)
#define TMR_C3_CNTR (TMRC_BASE + 0x35)
#define TMR_C3_HOLD (TMRC_BASE + 0x34)
#define TMR_C3_LOAD (TMRC_BASE + 0x33)
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