📄 mc56f835x.h
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#define ADCB_LST2 ( ADCB_BASE + 0x4 ) //Channel List Register 2
#define ADCB_SDIS ( ADCB_BASE + 0x5 ) //Sample Disable Register
#define ADCB_STAT ( ADCB_BASE + 0x6 ) //Status Register
#define ADCB_LSTAT ( ADCB_BASE + 0x7 ) //Limit Status Register
#define ADCB_ZCSTAT ( ADCB_BASE + 0x8 ) //Zero Crossing Status Register
#define ADCB_RSLT0 ( ADCB_BASE + 0x9 ) //Result Register 0
#define ADCB_RSLT1 ( ADCB_BASE + 0xA ) //Result Register 1
#define ADCB_RSLT2 ( ADCB_BASE + 0xB ) //Result Register 2
#define ADCB_RSLT3 ( ADCB_BASE + 0xC ) //Result Register 3
#define ADCB_RSLT4 ( ADCB_BASE + 0xD ) //Result Register 4
#define ADCB_RSLT5 ( ADCB_BASE + 0xE ) //Result Register 5
#define ADCB_RSLT6 ( ADCB_BASE + 0xF ) //Result Register 6
#define ADCB_RSLT7 ( ADCB_BASE + 0x10 ) //Result Register 7
#define ADCB_LLMT0 ( ADCB_BASE + 0x11 ) //Low Limit Register 0
#define ADCB_LLMT1 ( ADCB_BASE + 0x12 ) //Low Limit Register 1
#define ADCB_LLMT2 ( ADCB_BASE + 0x13 ) //Low Limit Register 2
#define ADCB_LLMT3 ( ADCB_BASE + 0x14 ) //Low Limit Register 3
#define ADCB_LLMT4 ( ADCB_BASE + 0x15 ) //Low Limit Register 4
#define ADCB_LLMT5 ( ADCB_BASE + 0x16 ) //Low Limit Register 5
#define ADCB_LLMT6 ( ADCB_BASE + 0x17 ) //Low Limit Register 6
#define ADCB_LLMT7 ( ADCB_BASE + 0x18 ) //Low Limit Register 7
#define ADCB_HLMT0 ( ADCB_BASE + 0x19 ) //High Limit Register 0
#define ADCB_HLMT1 ( ADCB_BASE + 0x1A ) //High Limit Register 1
#define ADCB_HLMT2 ( ADCB_BASE + 0x1B ) //High Limit Register 2
#define ADCB_HLMT3 ( ADCB_BASE + 0x1C ) //High Limit Register 3
#define ADCB_HLMT4 ( ADCB_BASE + 0x1D ) //High Limit Register 4
#define ADCB_HLMT5 ( ADCB_BASE + 0x1E ) //High Limit Register 5
#define ADCB_HLMT6 ( ADCB_BASE + 0x1F ) //High Limit Register 6
#define ADCB_HLMT7 ( ADCB_BASE + 0x20 ) //High Limit Register 7
#define ADCB_OFS0 ( ADCB_BASE + 0x21 ) //Offset Register 0
#define ADCB_OFS1 ( ADCB_BASE + 0x22 ) //Offset Register 1
#define ADCB_OFS2 ( ADCB_BASE + 0x23 ) //Offset Register 2
#define ADCB_OFS3 ( ADCB_BASE + 0x24 ) //Offset Register 3
#define ADCB_OFS4 ( ADCB_BASE + 0x25 ) //Offset Register 4
#define ADCB_OFS5 ( ADCB_BASE + 0x26 ) //Offset Register 5
#define ADCB_OFS6 ( ADCB_BASE + 0x27 ) //Offset Register 6
#define ADCB_OFS7 ( ADCB_BASE + 0x28 ) //Offset Register 7
#define ADCB_POWER ( ADCB_BASE + 0x29 ) //Power Control Register
#define ADCB_CAL ( ADCB_BASE + 0x2A ) //ADC Calibration Register
#define TSENSOR_CNTL ( TSENSOR_BASE + 0x0 ) //Control Register
#define SCI0_SCIBR ( SCI0_BASE + 0x0 ) //Baud Rate Register
#define SCI0_SCICR ( SCI0_BASE + 0x1 ) //Control Register
#define SCI0_SCISR ( SCI0_BASE + 0x3 ) //Status Register
#define SCI0_SCIDR ( SCI0_BASE + 0x4 ) //Data Register
#define SCI1_SCIBR ( SCI1_BASE + 0x0 ) //Baud Rate Register
#define SCI1_SCICR ( SCI1_BASE + 0x1 ) //Control Register
#define SCI1_SCISR ( SCI1_BASE + 0x3 ) //Status Register
#define SCI1_SCIDR ( SCI1_BASE + 0x4 ) //Data Register
/* modulul SPI0 */
#define SPI0_SPSCR ( SPI0_BASE + 0x0 ) //Status and Control Register
#define SPI0_SPDSR ( SPI0_BASE + 0x1 ) //Data Size Register
#define SPI0_SPDRR ( SPI0_BASE + 0x2 ) //Data Receive Register
#define SPI0_SPDTR ( SPI0_BASE + 0x3 ) //Data Transmitter Register
#define SPI1_SPSCR *(unsigned int *)( SPI1_BASE + 0x0 ) //Status and Control Register
#define SPI1_SPDSR *(unsigned int *)( SPI1_BASE + 0x1 ) //Data Size Register
#define SPI1_SPDRR *(unsigned int *)( SPI1_BASE + 0x2 ) //Data Receive Register
#define SPI1_SPDTR *(unsigned int *)( SPI1_BASE + 0x3 ) //Data Transmitter Register
#define COPCTL ( COP_BASE + 0x0 ) //Control Register
#define COPTO ( COP_BASE + 0x1 ) //Time Out Register
#define COPCTR ( COP_BASE + 0x2 ) //Counter Register
#define PLLCR ( CLKGEN_BASE + 0x0 ) //Control Register
#define PLLDB ( CLKGEN_BASE + 0x1 ) //Divide-By Register
#define PLLSR ( CLKGEN_BASE + 0x2 ) //Status Register
#define SHUTDOWN ( CLKGEN_BASE + 0x4 ) //Shutdown Register
#define OSCTL ( CLKGEN_BASE + 0x5 ) //Oscillator Control Register
/*Modulul GPIO A*/
#define GPIOA_PUR ( GPIOA_BASE + 0x0 ) //Pull-up Enable Register
#define GPIOA_DR *(volatile UInt16 *)( GPIOA_BASE + 0x1 ) //Data Register
#define GPIOA_DDR ( GPIOA_BASE + 0x2 ) //Data Direction Register
#define GPIOA_PER ( GPIOA_BASE + 0x3 ) //Peripheral Enable Register
#define GPIOA_IAR ( GPIOA_BASE + 0x4 ) //Interrupt Assert Register
#define GPIOA_IENR ( GPIOA_BASE + 0x5 ) //Interrupt Enable Register
#define GPIOA_IPOLR ( GPIOA_BASE + 0x6 ) //Interrupt Polarity Register
#define GPIOA_IPR ( GPIOA_BASE + 0x7 ) //Interrupt Pending Register
#define GPIOA_IESR ( GPIOA_BASE + 0x8 ) //Interrupt Edge-Sensitive Register
#define GPIOA_PPMODE ( GPIOA_BASE + 0x9 ) //Push-Pull Mode Register
#define GPIOA_RAWDATA ( GPIOA_BASE + 0xA ) //Raw Data Input Register
#define GPIOB_PUR ( GPIOB_BASE + 0x0 ) //Pull-up Enable Register
#define GPIOB_DR ( GPIOB_BASE + 0x1 ) //Data Register
#define GPIOB_DDR ( GPIOB_BASE + 0x2 ) //Data Direction Register
#define GPIOB_PER ( GPIOB_BASE + 0x3 ) //Peripheral Enable Register
#define GPIOB_IAR ( GPIOB_BASE + 0x4 ) //Interrupt Assert Register
#define GPIOB_IENR ( GPIOB_BASE + 0x5 ) //Interrupt Enable Register
#define GPIOB_IPOLR ( GPIOB_BASE + 0x6 ) //Interrupt Polarity Register
#define GPIOB_IPR ( GPIOB_BASE + 0x7 ) //Interrupt Pending Register
#define GPIOB_IESR ( GPIOB_BASE + 0x8 ) //Interrupt Edge-Sensitive Register
#define GPIOB_PPMODE ( GPIOB_BASE + 0x9 ) //Push-Pull Mode Register
#define GPIOB_RAWDATA ( GPIOB_BASE + 0xA ) //Raw Data Input Register
#define GPIOC_PUR ( GPIOC_BASE + 0x0 ) //Pull-up Enable Register
#define GPIOC_DR ( GPIOC_BASE + 0x1 ) //Data Register
#define GPIOC_DDR ( GPIOC_BASE + 0x2 ) //Data Direction Register
#define GPIOC_PER ( GPIOC_BASE + 0x3 ) //Peripheral Enable Register
#define GPIOC_IAR ( GPIOC_BASE + 0x4 ) //Interrupt Assert Register
#define GPIOC_IENR ( GPIOC_BASE + 0x5 ) //Interrupt Enable Register
#define GPIOC_IPOLR ( GPIOC_BASE + 0x6 ) //Interrupt Polarity Register
#define GPIOC_IPR ( GPIOC_BASE + 0x7 ) //Interrupt Pending Register
#define GPIOC_IESR ( GPIOC_BASE + 0x8 ) //Interrupt Edge-Sensitive Register
#define GPIOC_PPMODE ( GPIOC_BASE + 0x9 ) //Push-Pull Mode Register
#define GPIOC_RAWDATA ( GPIOC_BASE + 0xA ) //Raw Data Input Register
#define GPIOD_PUR ( GPIOD_BASE + 0x0 ) //Pull-up Enable Register
#define GPIOD_DR ( GPIOD_BASE + 0x1 ) //Data Register
#define GPIOD_DDR ( GPIOD_BASE + 0x2 ) //Data Direction Register
#define GPIOD_PER ( GPIOD_BASE + 0x3 ) //Peripheral Enable Register
#define GPIOD_IAR ( GPIOD_BASE + 0x4 ) //Interrupt Assert Register
#define GPIOD_IENR ( GPIOD_BASE + 0x5 ) //Interrupt Enable Register
#define GPIOD_IPOLR ( GPIOD_BASE + 0x6 ) //Interrupt Polarity Register
#define GPIOD_IPR ( GPIOD_BASE + 0x7 ) //Interrupt Pending Register
#define GPIOD_IESR ( GPIOD_BASE + 0x8 ) //Interrupt Edge-Sensitive Register
#define GPIOD_PPMODE ( GPIOD_BASE + 0x9 ) //Push-Pull Mode Register
#define GPIOD_RAWDATA ( GPIOD_BASE + 0xA ) //Raw Data Input Register
#define GPIOE_PUR ( GPIOE_BASE + 0x0 ) //Pull-up Enable Register
#define GPIOE_DR ( GPIOE_BASE + 0x1 ) //Data Register
#define GPIOE_DDR ( GPIOE_BASE + 0x2 ) //Data Direction Register
#define GPIOE_PER ( GPIOE_BASE + 0x3 ) //Peripheral Enable Register
#define GPIOE_IAR ( GPIOE_BASE + 0x4 ) //Interrupt Assert Register
#define GPIOE_IENR ( GPIOE_BASE + 0x5 ) //Interrupt Enable Register
#define GPIOE_IPOLR ( GPIOE_BASE + 0x6 ) //Interrupt Polarity Register
#define GPIOE_IPR ( GPIOE_BASE + 0x7 ) //Interrupt Pending Register
#define GPIOE_IESR ( GPIOE_BASE + 0x8 ) //Interrupt Edge-Sensitive Register
#define GPIOE_PPMODE ( GPIOE_BASE + 0x9 ) //Push-Pull Mode Register
#define GPIOE_RAWDATA ( GPIOE_BASE + 0xA ) //Raw Data Input Register
#define GPIOF_PUR ( GPIOF_BASE + 0x0 ) //Pull-up Enable Register
#define GPIOF_DR ( GPIOF_BASE + 0x1 ) //Data Register
#define GPIOF_DDR ( GPIOF_BASE + 0x2 ) //Data Direction Register
#define GPIOF_PER ( GPIOF_BASE + 0x3 ) //Peripheral Enable Register
#define GPIOF_IAR ( GPIOF_BASE + 0x4 ) //Interrupt Assert Register
#define GPIOF_IENR ( GPIOF_BASE + 0x5 ) //Interrupt Enable Register
#define GPIOF_IPOLR ( GPIOF_BASE + 0x6 ) //Interrupt Polarity Register
#define GPIOF_IPR ( GPIOF_BASE + 0x7 ) //Interrupt Pending Register
#define GPIOF_IESR ( GPIOF_BASE + 0x8 ) //Interrupt Edge-Sensitive Register
#define GPIOF_PPMODE ( GPIOF_BASE + 0x9 ) //Push-Pull Mode Register
#define GPIOF_RAWDATA ( GPIOF_BASE + 0xA ) //Raw Data Input Register
#define SIM_CONTROL ( SIM_BASE + 0x0 ) //Control Register
#define SIM_RSTSTS ( SIM_BASE + 0x1 ) //Reset Status Register
#define SIM_SCR0 ( SIM_BASE + 0x2 ) //Software Control Register 0
#define SIM_SCR1 ( SIM_BASE + 0x3 ) //Software Control Register 1
#define SIM_SCR2 ( SIM_BASE + 0x4 ) //Software Control Register 2
#define SIM_SCR3 ( SIM_BASE + 0x5 ) //Software Control Register 3
#define SIM_MSH_ID ( SIM_BASE + 0x6 ) //Most Significant Half JTAG ID
#define SIM_LSH_ID ( SIM_BASE + 0x7 ) //Least Significant Half JTAG ID
#define SIM_PUDR ( SIM_BASE + 0x8 ) //Pull-up Disable Register
#define SIM_CLKOSR ( SIM_BASE + 0xA ) //Clock Out Select Register
#define SIM_GPS ( SIM_BASE + 0xB ) //Quad Decoder 1 / Timer B / SPI 1 Select Register
#define SIM_PCE ( SIM_BASE + 0xC ) //Peripheral Clock Enable Register
#define SIM_ISALH ( SIM_BASE + 0xD ) //I/O Short Address Location High Register
#define SIM_ISALL ( SIM_BASE + 0xE ) //I/O Short Address Location Low Register
#define SIM_PCE2 ( SIM_BASE + 0xF ) //Peripheral Clock Enable Register 2
#define LVI_CONTROL ( LVI_BASE + 0x0 ) //Control Register
#define LVI_STATUS ( LVI_BASE + 0x1 ) //Status Register
#define FMCLKD ( FM_BASE + 0x0 ) //Clock Divider Register
#define FMMCR ( FM_BASE + 0x1 ) //Module Control Register
#define FMSECH ( FM_BASE + 0x3 ) //Security High Half Register
#define FMSECL ( FM_BASE + 0x4 ) //Security Low Half Register
#define FMPROT ( FM_BASE + 0x10 ) //Protection Register (Banked)
#define FMPROTB ( FM_BASE + 0x11 ) //Protection Boot Register (Banked)
#define FMUSTAT ( FM_BASE + 0x13 ) //User Status Register (Banked)
#define FMCMD ( FM_BASE + 0x14 ) //Command Register (Banked)
#define FMOPT0 ( FM_BASE + 0x1A ) //16-Bit Information Option Register 0
#define FMOPT1 ( FM_BASE + 0x1B ) //16-Bit Information Option Register 1
#define FMOPT2 ( FM_BASE + 0x1C ) //16-Bit Information Option Register 2
#define FCMCR ( FC_BASE + 0x0 ) //Module Configuration Register
#define FCCTL0 ( FC_BASE + 0x3 ) //Control Register 0 Register
#define FCCTL1 ( FC_BASE + 0x4 ) //Control Register 1 Register
#define FCTMR ( FC_BASE + 0x5 ) //Free-Running Timer Register
#define FCMAXMB ( FC_BASE + 0x6 ) //Maximum Message Buffer Configuration Register
#define FCRXGMASK_H ( FC_BASE + 0x8 ) //Receive Global Mask High Register
#define FCRXGMASK_L ( FC_BASE + 0x9 ) //Receive Global Mask Low Register
#define FCRX14MASK_H ( FC_BASE + 0xA ) //Receive Buffer 14 Mask High Register
#define FCRX14MASK_L ( FC_BASE + 0xB ) //Receive Buffer 14 Mask Low Register
#define FCRX15MASK_H ( FC_BASE + 0xC ) //Receive Buffer 15 Mask High Register
#define FCRX15MASK_L ( FC_BASE + 0xD ) //Receive Buffer 15 Mask Low Register
#define FCSTATUS ( FC_BASE + 0x10 ) //Error and Status Register
#define FCIMASK1 ( FC_BASE + 0x11 ) //Interrupt Masks 1 Register
#define FCIFLAG1 ( FC_BASE + 0x12 ) //Interrupt Flags 1 Register
#define FCR__T_ERROR_CNTRS ( FC_BASE + 0x13 ) //Receive and Transmit Error Counters Register
#define FCMB0_CONTROL ( FC_BASE + 0x40 ) //Message Buffer 0 Control / Status Register
#define FCMB0_ID_HIGH ( FC_BASE + 0x41 ) //Message Buffer 0 ID High Register
#define FCMB0_ID_LOW ( FC_BASE + 0x42 ) //Message Buffer 0 ID Low Register
#define FCMB0_DATA ( FC_BASE + 0x43 ) //Message Buffer 0 Data Register
#define FCMSB1_CONTROL ( FC_BASE + 0x48 ) //Message Buffer 1 Control / Status Register
#define FCMSB1_ID_HIGH ( FC_BASE + 0x49 ) //Message Buffer 1 ID High Register
#define FCMSB1_ID_LOW ( FC_BASE + 0x4A ) //Message Buffer 1 ID Low Register
#define FCMB1_DATA ( FC_BASE + 0x4B ) //Message Buffer 1 Data Register
#define FCMB2_CONTROL ( FC_BASE + 0x50 ) //Message Buffer 2 Control / Status Register
#define FCMB2_ID_HIGH ( FC_BASE + 0x51 ) //Message Buffer 2 ID High Register
#define FCMB2_ID_LOW ( FC_BASE + 0x52 ) //Message Buffer 2 ID Low Register
#define FCMB2_DATA ( FC_BASE + 0x53 ) //Message Buffer 2 Data Register
#define FCMB3_CONTROL ( FC_BASE + 0x58 ) //Message Buffer 3 Control / Status Register
#define FCMB3_ID_HIGH ( FC_BASE + 0x59 ) //Message Buffer 3 ID High Register
#define FCMB3_ID_LOW ( FC_BASE + 0x5A ) //Message Buffer 3 ID Low Register
#define FCMB3_DATA ( FC_BASE + 0x5B ) //Message Buffer 3 Data Register
#define FCMB4_CONTROL ( FC_BASE + 0x60 ) //Message Buffer 4 Control / Status Register
#define FCMB4_ID_HIGH ( FC_BASE + 0x61 ) //Message Buffer 4 ID High Register
#define FCMB4_ID_LOW ( FC_BASE + 0x62 ) //Message Buffer 4 ID Low Register
#define FCMB4_DATA ( FC_BASE + 0x63 ) //Message Buffer 4 Data Register
#define FCMB5_CONTROL ( FC_BASE + 0x68 ) //Message Buffer 5 Control / Status Register
#define FCMB5_ID_HIGH ( FC_BASE + 0x69 ) //Message Buffer 5 ID High Register
#define FCMB5_ID_LOW ( FC_BASE + 0x6A ) //Message Buffer 5 ID Low Register
#define FCMB5_DATA ( FC_BASE + 0x6B ) //Message Buffer 5 Data Register
#define FCMB6_CONTROL ( FC_BASE + 0x70 ) //Message Buffer 6 Control / Status Register
#define FCMB6_ID_HIGH ( FC_BASE + 0x71 ) //Message Buffer 6 ID High Register
#define FCMB6_ID_LOW ( FC_BASE + 0x72 ) //Message Buffer 6 ID Low Register
#define FCMB6_DATA ( FC_BASE + 0x73 ) //Message Buffer 6 Data Register
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