📄 mc56f835x.h
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#define TMRC2_LOAD ( TMRC_BASE + 0x23 ) //Load Register
#define TMRC2_HOLD ( TMRC_BASE + 0x24 ) //Hold Register
#define TMRC2_CNTR ( TMRC_BASE + 0x25 ) //Counter Register
#define TMRC2_CTRL ( TMRC_BASE + 0x26 ) //Control Register
#define TMRC2_SCR ( TMRC_BASE + 0x27 ) //Status and Control Register
#define TMRC2_CMPLD1 ( TMRC_BASE + 0x28 ) //Comparator Load Register 1
#define TMRC2_CMPLD2 ( TMRC_BASE + 0x29 ) //Comparator Load Register 2
#define TMRC2_COMSCR ( TMRC_BASE + 0x2A ) //Comparator Status and Control Register
// --> Timer C canal 3
#define TMRC3_CMP1 ( TMRC_BASE + 0x30 ) //Compare Register 1
#define TMRC3_CMP2 ( TMRC_BASE + 0x31 ) //Compare Register 2
#define TMRC3_CAP ( TMRC_BASE + 0x32 ) //Capture Register
#define TMRC3_LOAD ( TMRC_BASE + 0x33 ) //Load Register
#define TMRC3_HOLD ( TMRC_BASE + 0x34 ) //Hold Register
#define TMRC3_CNTR ( TMRC_BASE + 0x35 ) //Counter Register
#define TMRC3_CTRL ( TMRC_BASE + 0x36 ) //Control Register
#define TMRC3_SCR ( TMRC_BASE + 0x37 ) //Status and Control Register
#define TMRC3_CMPLD1 ( TMRC_BASE + 0x38 ) //Comparator Load Register 1
#define TMRC3_CMPLD2 ( TMRC_BASE + 0x39 ) //Comparator Load Register 2
#define TMRC3_COMSCR ( TMRC_BASE + 0x3A ) //Comparator Status and Control Register
/* Registri pentru configurarea timerului D */
// --> Timer D canal 0
#define TMRD0_CMP1 ( TMRD_BASE + 0x0 ) //Compare Register 1
#define TMRD0_CMP2 ( TMRD_BASE + 0x1 ) //Compare Register 2
#define TMRD0_CAP ( TMRD_BASE + 0x2 ) //Capture Register
#define TMRD0_LOAD ( TMRD_BASE + 0x3 ) //Load Register
#define TMRD0_HOLD ( TMRD_BASE + 0x4 ) //Hold Register
#define TMRD0_CNTR ( TMRD_BASE + 0x5 ) //Counter Register
#define TMRD0_CTRL ( TMRD_BASE + 0x6 ) //Control Register
#define TMRD0_SCR ( TMRD_BASE + 0x7 ) //Status and Control Register
#define TMRD0_CMPLD1 ( TMRD_BASE + 0x8 ) //Comparator Load Register 1
#define TMRD0_CMPLD2 ( TMRD_BASE + 0x9 ) //Comparator Load Register 2
#define TMRD0_COMSCR ( TMRD_BASE + 0xA ) //Comparator Status and Control Register
// --> Timer D canal 1
#define TMRD1_CMP1 ( TMRD_BASE + 0x10 ) //Compare Register 1
#define TMRD1_CMP2 ( TMRD_BASE + 0x11 ) //Compare Register 2
#define TMRD1_CAP ( TMRD_BASE + 0x12 ) //Capture Register
#define TMRD1_LOAD ( TMRD_BASE + 0x13 ) //Load Register
#define TMRD1_HOLD ( TMRD_BASE + 0x14 ) //Hold Register
#define TMRD1_CNTR ( TMRD_BASE + 0x15 ) //Counter Register
#define TMRD1_CTRL ( TMRD_BASE + 0x16 ) //Control Register
#define TMRD1_SCR ( TMRD_BASE + 0x17 ) //Status and Control Register
#define TMRD1_CMPLD1 ( TMRD_BASE + 0x18 ) //Comparator Load Register 1
#define TMRD1_CMPLD2 ( TMRD_BASE + 0x19 ) //Comparator Load Register 2
#define TMRD1_COMSCR ( TMRD_BASE + 0x1A ) //Comparator Status and Control Register
// --> Timer D canal 2
#define TMRD2_CMP1 ( TMRD_BASE + 0x20 ) //Compare Register 1
#define TMRD2_CMP2 ( TMRD_BASE + 0x21 ) //Compare Register 2
#define TMRD2_CAP ( TMRD_BASE + 0x22 ) //Capture Register
#define TMRD2_LOAD ( TMRD_BASE + 0x23 ) //Load Register
#define TMRD2_HOLD ( TMRD_BASE + 0x24 ) //Hold Register
#define TMRD2_CNTR ( TMRD_BASE + 0x25 ) //Counter Register
#define TMRD2_CTRL ( TMRD_BASE + 0x26 ) //Control Register
#define TMRD2_SCR ( TMRD_BASE + 0x27 ) //Status and Control Register
#define TMRD2_CMPLD1 ( TMRD_BASE + 0x28 ) //Comparator Load Register 1
#define TMRD2_CMPLD2 ( TMRD_BASE + 0x29 ) //Comparator Load Register 2
#define TMRD2_COMSCR ( TMRD_BASE + 0x2A ) //Comparator Status and Control Register
// --> Timer D canal 3
#define TMRD3_CMP1 ( TMRD_BASE + 0x30 ) //Compare Register 1
#define TMRD3_CMP2 ( TMRD_BASE + 0x31 ) //Compare Register 2
#define TMRD3_CAP ( TMRD_BASE + 0x32 ) //Capture Register
#define TMRD3_LOAD ( TMRD_BASE + 0x33 ) //Load Register
#define TMRD3_HOLD ( TMRD_BASE + 0x34 ) //Hold Register
#define TMRD3_CNTR ( TMRD_BASE + 0x35 ) //Counter Register
#define TMRD3_CTRL ( TMRD_BASE + 0x36 ) //Control Register
#define TMRD3_SCR ( TMRD_BASE + 0x37 ) //Status and Control Register
#define TMRD3_CMPLD1 ( TMRD_BASE + 0x38 ) //Comparator Load Register 1
#define TMRD3_CMPLD2 ( TMRD_BASE + 0x39 ) //Comparator Load Register 2
#define TMRD3_COMSCR ( TMRD_BASE + 0x3A ) //Comparator Status and Control Register
#define PWMA_PMCTL ( PWMA_BASE + 0x0 ) //Control Register
#define PWMA_PMFCTL ( PWMA_BASE + 0x1 ) //Fault Control Register
#define PWMA_PMFSA ( PWMA_BASE + 0x2 ) //Fault Status Acknowledge Register
#define PWMA_PMOUT ( PWMA_BASE + 0x3 ) //Output Control Register
#define PWMA_PMCNT ( PWMA_BASE + 0x4 ) //Counter Register
#define PWMA_PWMCM ( PWMA_BASE + 0x5 ) //Counter Modulo Register
#define PWMA_PWMVAL0 ( PWMA_BASE + 0x6 ) //Value Register 0
#define PWMA_PWMVAL1 ( PWMA_BASE + 0x7 ) //Value Register 1
#define PWMA_PWMVAL2 ( PWMA_BASE + 0x8 ) //Value Register 2
#define PWMA_PWMVAL3 ( PWMA_BASE + 0x9 ) //Value Register 3
#define PWMA_PWMVAL4 ( PWMA_BASE + 0xA ) //Value Register 4
#define PWMA_PWMVAL5 ( PWMA_BASE + 0xB ) //Value Register 5
#define PWMA_PMDEADTM ( PWMA_BASE + 0xC ) //Dead Time Register
#define PWMA_PMDISMAP1 ( PWMA_BASE + 0xD ) //Disable Mapping Register 1
#define PWMA_PMDISMAP2 ( PWMA_BASE + 0xE ) //Disable Mapping Register 2
#define PWMA_PMCFG ( PWMA_BASE + 0xF ) //Configure Register
#define PWMA_PMCCR ( PWMA_BASE + 0x10 ) //Channel Control Register
#define PWMA_PMPORT ( PWMA_BASE + 0x11 ) //Port Register
#define PWMA_PMICCR ( PWMA_BASE + 0x12 ) //PWM Internal Correction Control Register
#define PWMB_PMCTL ( PWMB_BASE + 0x0 ) //Control Register
#define PWMB_PMFCTL ( PWMB_BASE + 0x1 ) //Fault Control Register
#define PWMB_PMFSA ( PWMB_BASE + 0x2 ) //Fault Status Acknowledge Register
#define PWMB_PMOUT ( PWMB_BASE + 0x3 ) //Output Control Register
#define PWMB_PMCNT ( PWMB_BASE + 0x4 ) //Counter Register
#define PWMB_PWMCM ( PWMB_BASE + 0x5 ) //Counter Modulo Register
#define PWMB_PWMVAL0 ( PWMB_BASE + 0x6 ) //Value Register 0
#define PWMB_PWMVAL1 ( PWMB_BASE + 0x7 ) //Value Register 1
#define PWMB_PWMVAL2 ( PWMB_BASE + 0x8 ) //Value Register 2
#define PWMB_PWMVAL3 ( PWMB_BASE + 0x9 ) //Value Register 3
#define PWMB_PWMVAL4 ( PWMB_BASE + 0xA ) //Value Register 4
#define PWMB_PWMVAL5 ( PWMB_BASE + 0xB ) //Value Register 5
#define PWMB_PMDEADTM ( PWMB_BASE + 0xC ) //Dead Time Register
#define PWMB_PMDISMAP1 ( PWMB_BASE + 0xD ) //Disable Mapping Register 1
#define PWMB_PMDISMAP2 ( PWMB_BASE + 0xE ) //Disable Mapping Register 2
#define PWMB_PMCFG ( PWMB_BASE + 0xF ) //Configure Register
#define PWMB_PMCCR ( PWMB_BASE + 0x10 ) //Channel Control Register
#define PWMB_PMPORT ( PWMB_BASE + 0x11 ) //Port Register
#define PWMB_PMICCR ( PWMB_BASE + 0x12 ) //PWM Internal Correction Control Register
#define DEC0_DECCR ( DEC0_BASE + 0x0 ) //Decoder Control Register
#define DEC0_FIR ( DEC0_BASE + 0x1 ) //Filter Interval Register
#define DEC0_WTR ( DEC0_BASE + 0x2 ) //Watchdog Time-out Register
#define DEC0_POSD ( DEC0_BASE + 0x3 ) //Position Difference Counter Register
#define DEC0_POSDH ( DEC0_BASE + 0x4 ) //Position Difference Counter Hold Register
#define DEC0_REV ( DEC0_BASE + 0x5 ) //Revolution Counter Register
#define DEC0_REVH ( DEC0_BASE + 0x6 ) //Revolution Hold Register
#define DEC0_UPOS ( DEC0_BASE + 0x7 ) //Upper Position Counter Register
#define DEC0_LPOS ( DEC0_BASE + 0x8 ) //Lower Position Counter Register
#define DEC0_UPOSH ( DEC0_BASE + 0x9 ) //Upper Position Hold Register
#define DEC0_LPOSH ( DEC0_BASE + 0xA ) //Lower Position Hold Register
#define DEC0_UIR ( DEC0_BASE + 0xB ) //Upper Initialization Register
#define DEC0_LIR ( DEC0_BASE + 0xC ) //Lower Initialization Register
#define DEC0_IMR ( DEC0_BASE + 0xD ) //Input Monitor Register
#define DEC1_DECCR ( DEC1_BASE + 0x0 ) //Decoder Control Register
#define DEC1_FIR ( DEC1_BASE + 0x1 ) //Filter Interval Register
#define DEC1_WTR ( DEC1_BASE + 0x2 ) //Watchdog Time-out Register
#define DEC1_POSD ( DEC1_BASE + 0x3 ) //Position Difference Counter Register
#define DEC1_POSDH ( DEC1_BASE + 0x4 ) //Position Difference Counter Hold Register
#define DEC1_REV ( DEC1_BASE + 0x5 ) //Revolution Counter Register
#define DEC1_REVH ( DEC1_BASE + 0x6 ) //Revolution Hold Register
#define DEC1_UPOS ( DEC1_BASE + 0x7 ) //Upper Position Counter Register
#define DEC1_LPOS ( DEC1_BASE + 0x8 ) //Lower Position Counter Register
#define DEC1_UPOSH ( DEC1_BASE + 0x9 ) //Upper Position Hold Register
#define DEC1_LPOSH ( DEC1_BASE + 0xA ) //Lower Position Hold Register
#define DEC1_UIR ( DEC1_BASE + 0xB ) //Upper Initialization Register
#define DEC1_LIR ( DEC1_BASE + 0xC ) //Lower Initialization Register
#define DEC1_IMR ( DEC1_BASE + 0xD ) //Input Monitor Register
#define IPR0 ( ITCN_BASE + 0x0 ) //Interrupt Priority Register 0
#define IPR1 ( ITCN_BASE + 0x1 ) //Interrupt Priority Register 1
#define IPR2 ( ITCN_BASE + 0x2 ) //Interrupt Priority Register 2
#define IPR3 ( ITCN_BASE + 0x3 ) //Interrupt Priority Register 3
#define IPR4 ( ITCN_BASE + 0x4 ) //Interrupt Priority Register 4
#define IPR5 ( ITCN_BASE + 0x5 ) //Interrupt Priority Register 5
#define IPR6 ( ITCN_BASE + 0x6 ) //Interrupt Priority Register 6
#define IPR7 ( ITCN_BASE + 0x7 ) //Interrupt Priority Register 7
#define IPR8 ( ITCN_BASE + 0x8 ) //Interrupt Priority Register 8
#define IPR9 ( ITCN_BASE + 0x9 ) //Interrupt Priority Register 9
#define VBA ( ITCN_BASE + 0xA ) //Vector Base Address Register
#define FIM0 ( ITCN_BASE + 0xB ) //Fast Interrupt Match Register 0
#define FIVAL0 ( ITCN_BASE + 0xC ) //Fast Interrupt Vector Address Low 0 Register
#define FIVAH0 ( ITCN_BASE + 0xD ) //Fast Interrupt Vector Address High 0 Register
#define FIM1 ( ITCN_BASE + 0xE ) //Fast Interrupt Match Register 1
#define FIVAL1 ( ITCN_BASE + 0xF ) //Fast Interrupt Vector Address Low 1 Register
#define FIVAH1 ( ITCN_BASE + 0x10 ) //Fast Interrupt Vector Address High 1 Register
#define IRQP0 ( ITCN_BASE + 0x11 ) //IRQ Pending Register 0
#define IRQP1 ( ITCN_BASE + 0x12 ) //IRQ Pending Register 1
#define IRQP2 ( ITCN_BASE + 0x13 ) //IRQ Pending Register 2
#define IRQP3 ( ITCN_BASE + 0x14 ) //IRQ Pending Register 3
#define IRQP4 ( ITCN_BASE + 0x15 ) //IRQ Pending Register 4
#define IRQP5 ( ITCN_BASE + 0x16 ) //IRQ Pending Register 5
#define ICTL ( ITCN_BASE + 0x1D ) //Interrupt Control Register
#define IPR10 ( ITCN_BASE + 0x1F ) //Interrupt Priority Register 10
#define ADCA_CR1 ( ADCA_BASE + 0x0 ) //Control Register 1
#define ADCA_CR2 ( ADCA_BASE + 0x1 ) //Control Register 2
#define ADCA_ZCC ( ADCA_BASE + 0x2 ) //Zero Crossing Control Register
#define ADCA_LST1 ( ADCA_BASE + 0x3 ) //Channel List Register 1
#define ADCA_LST2 ( ADCA_BASE + 0x4 ) //Channel List Register 2
#define ADCA_SDIS ( ADCA_BASE + 0x5 ) //Sample Disable Register
#define ADCA_STAT ( ADCA_BASE + 0x6 ) //Status Register
#define ADCA_LSTAT ( ADCA_BASE + 0x7 ) //Limit Status Register
#define ADCA_ZCSTAT ( ADCA_BASE + 0x8 ) //Zero Crossing Status Register
#define ADCA_RSLT0 ( ADCA_BASE + 0x9 ) //Result Register 0
#define ADCA_RSLT1 ( ADCA_BASE + 0xA ) //Result Register 1
#define ADCA_RSLT2 ( ADCA_BASE + 0xB ) //Result Register 2
#define ADCA_RSLT3 ( ADCA_BASE + 0xC ) //Result Register 3
#define ADCA_RSLT4 ( ADCA_BASE + 0xD ) //Result Register 4
#define ADCA_RSLT5 ( ADCA_BASE + 0xE ) //Result Register 5
#define ADCA_RSLT6 ( ADCA_BASE + 0xF ) //Result Register 6
#define ADCA_RSLT7 ( ADCA_BASE + 0x10 ) //Result Register 7
#define ADCA_LLMT0 ( ADCA_BASE + 0x11 ) //Low Limit Register 0
#define ADCA_LLMT1 ( ADCA_BASE + 0x12 ) //Low Limit Register 1
#define ADCA_LLMT2 ( ADCA_BASE + 0x13 ) //Low Limit Register 2
#define ADCA_LLMT3 ( ADCA_BASE + 0x14 ) //Low Limit Register 3
#define ADCA_LLMT4 ( ADCA_BASE + 0x15 ) //Low Limit Register 4
#define ADCA_LLMT5 ( ADCA_BASE + 0x16 ) //Low Limit Register 5
#define ADCA_LLMT6 ( ADCA_BASE + 0x17 ) //Low Limit Register 6
#define ADCA_LLMT7 ( ADCA_BASE + 0x18 ) //Low Limit Register 7
#define ADCA_HLMT0 ( ADCA_BASE + 0x19 ) //High Limit Register 0
#define ADCA_HLMT1 ( ADCA_BASE + 0x1A ) //High Limit Register 1
#define ADCA_HLMT2 ( ADCA_BASE + 0x1B ) //High Limit Register 2
#define ADCA_HLMT3 ( ADCA_BASE + 0x1C ) //High Limit Register 3
#define ADCA_HLMT4 ( ADCA_BASE + 0x1D ) //High Limit Register 4
#define ADCA_HLMT5 ( ADCA_BASE + 0x1E ) //High Limit Register 5
#define ADCA_HLMT6 ( ADCA_BASE + 0x1F ) //High Limit Register 6
#define ADCA_HLMT7 ( ADCA_BASE + 0x20 ) //High Limit Register 7
#define ADCA_OFS0 ( ADCA_BASE + 0x21 ) //Offset Register 0
#define ADCA_OFS1 ( ADCA_BASE + 0x22 ) //Offset Register 1
#define ADCA_OFS2 ( ADCA_BASE + 0x23 ) //Offset Register 2
#define ADCA_OFS3 ( ADCA_BASE + 0x24 ) //Offset Register 3
#define ADCA_OFS4 ( ADCA_BASE + 0x25 ) //Offset Register 4
#define ADCA_OFS5 ( ADCA_BASE + 0x26 ) //Offset Register 5
#define ADCA_OFS6 ( ADCA_BASE + 0x27 ) //Offset Register 6
#define ADCA_OFS7 ( ADCA_BASE + 0x28 ) //Offset Register 7
#define ADCA_POWER ( ADCA_BASE + 0x29 ) //Power Control Register
#define ADCA_CAL ( ADCA_BASE + 0x2A ) //ADC Calibration Register
#define ADCB_CR1 ( ADCB_BASE + 0x0 ) //Control Register 1
#define ADCB_CR2 ( ADCB_BASE + 0x1 ) //Control Register 2
#define ADCB_ZCC ( ADCB_BASE + 0x2 ) //Zero Crossing Control Register
#define ADCB_LST1 ( ADCB_BASE + 0x3 ) //Channel List Register 1
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