mc56f835x.h

DSP56F800e HYBRID Controller

#define OESCR		0xFFFF8A
#define OBCNTR		0xFFFF8E
#define OBMSK		0xFFFF90
#define OBAR2		0xFFFF92
#define OBAR1		0xFFFF94
#define OBCR		0xFFFF96
#define OTB			0xFFFF9B
#define OTBPR		0xFFFF9A
#define OTBCR		0xFFFF9B
#define OBASE		0xFFFF9C
#define OSR			0xFFFF9D
#define OSCNTR		0xFFFF9E
#define OCR			0xFFFFA0
#define OCLSR		0xFFFFFC
#define OTXRXSR		0xFFFFFD
#define OTX_ORX		0xFFFFFE
#define OTX1_ORX1	0xFFFFFF

// High Level Peripheral Memory Interface
#define   EMI_BASE        0xF020     //  External Memory Interface
#define   TMRA_BASE       0xF040     //  Timer A
#define   TMRB_BASE       0xF080     //  Timer B
#define   TMRC_BASE       0xF0C0     //  Timer C
#define   TMRD_BASE       0xF100     //  Timer D
#define   PWMA_BASE       0xF140     //  PWM A
#define   PWMB_BASE       0xF160     //  PWM B
#define   DEC0_BASE       0xF180     //  Quadrature Decoder 0
#define   DEC1_BASE       0xF190     //  Quadrature Decoder 1
#define   ITCN_BASE       0xF1A0     //  ITCN
#define   ADCA_BASE       0xF200     //  ADC A
#define   ADCB_BASE       0xF240     //  ADC B
#define   TSENSOR_BASE    0xF270     //  Temperature Sensor
#define   SCI0_BASE       0xF280     //  SCI #0
#define   SCI1_BASE       0xF290     //  SCI #1
#define   SPI0_BASE       0xF2A0     //  SPI #0
#define   SPI1_BASE       0xF2B0     //  SPI #1
#define   COP_BASE        0xF2C0     //  COP
#define   CLKGEN_BASE     0xF2D0     //  PLL, OSC
#define   GPIOA_BASE      0xF2E0     //  GPIO Port A
#define   GPIOB_BASE      0xF300     //  GPIO Port B
#define   GPIOC_BASE      0xF310     //  GPIO Port C
#define   GPIOD_BASE      0xF320     //  GPIO Port D
#define   GPIOE_BASE      0xF330     //  GPIO Port E
#define   GPIOF_BASE      0xF340     //  GPIO Port F
#define   SIM_BASE        0xF350     //  SIM
#define   LVI_BASE        0xF360     //  Power Supervisor
#define   FM_BASE         0xF400     //  FM
#define   FC_BASE         0xF800     //  FlexCAN


#define  CSBAR0                 ( EMI_BASE      + 0x0  )  //Chip Select Base Address Register 0
#define  CSBAR1                 ( EMI_BASE      + 0x1  )  //Chip Select Base Address Register 1
#define  CSBAR2                 ( EMI_BASE      + 0x2  )  //Chip Select Base Address Register 2
#define  CSBAR3                 ( EMI_BASE      + 0x3  )  //Chip Select Base Address Register 3
#define  CSBAR4                 ( EMI_BASE      + 0x4  )  //Chip Select Base Address Register 4
#define  CSBAR5                 ( EMI_BASE      + 0x5  )  //Chip Select Base Address Register 5
#define  CSBAR6                 ( EMI_BASE      + 0x6  )  //Chip Select Base Address Register 6
#define  CSBAR7                 ( EMI_BASE      + 0x7  )  //Chip Select Base Address Register 7
#define  CSOR0                  ( EMI_BASE      + 0x8  )  //Chip Select Option Register 0
#define  CSOR1                  ( EMI_BASE      + 0x9  )  //Chip Select Option Register 1
#define  CSOR2                  ( EMI_BASE      + 0xA  )  //Chip Select Option Register 2
#define  CSOR3                  ( EMI_BASE      + 0xB  )  //Chip Select Option Register 3
#define  CSOR4                  ( EMI_BASE      + 0xC  )  //Chip Select Option Register 4
#define  CSOR5                  ( EMI_BASE      + 0xD  )  //Chip Select Option Register 5
#define  CSOR6                  ( EMI_BASE      + 0xE  )  //Chip Select Option Register 6
#define  CSOR7                  ( EMI_BASE      + 0xF  )  //Chip Select Option Register 7
#define  CSTC0                  ( EMI_BASE      + 0x10 )  //Chip Select Timing Control Register 0
#define  CSTC1                  ( EMI_BASE      + 0x11 )  //Chip Select Timing Control Register 1
#define  CSTC2                  ( EMI_BASE      + 0x12 )  //Chip Select Timing Control Register 2
#define  CSTC3                  ( EMI_BASE      + 0x13 )  //Chip Select Timing Control Register 3
#define  CSTC4                  ( EMI_BASE      + 0x14 )  //Chip Select Timing Control Register 4
#define  CSTC5                  ( EMI_BASE      + 0x15 )  //Chip Select Timing Control Register 5
#define  CSTC6                  ( EMI_BASE      + 0x16 )  //Chip Select Timing Control Register 6
#define  CSTC7                  ( EMI_BASE      + 0x17 )  //Chip Select Timing Control Register 7
#define  BCR                    ( EMI_BASE      + 0x18 )  //Bus Control Register


                /*  Registri pentru configurarea timerului A   */

//    --> Timer A canal 0
#define  TMRA0_CMP1             ( TMRA_BASE     + 0x0  )  //Compare Register 1
#define  TMRA0_CMP2             ( TMRA_BASE     + 0x1  )  //Compare Register 2
#define  TMRA0_CAP              ( TMRA_BASE     + 0x2  )  //Capture Register
#define  TMRA0_LOAD             ( TMRA_BASE     + 0x3  )  //Load Register
#define  TMRA0_HOLD             ( TMRA_BASE     + 0x4  )  //Hold Register
#define  TMRA0_CNTR             ( TMRA_BASE     + 0x5  )  //Counter Register
#define  TMRA0_CTRL             ( TMRA_BASE     + 0x6  )  //Control Register
#define  TMRA0_SCR              ( TMRA_BASE     + 0x7  )  //Status and Control Register
#define  TMRA0_CMPLD1           ( TMRA_BASE     + 0x8  )  //Comparator Load Register 1
#define  TMRA0_CMPLD2           ( TMRA_BASE     + 0x9  )  //Comparator Load Register 2
#define  TMRA0_COMSCR           ( TMRA_BASE     + 0xA  )  //Comparator Status and Control Register
//    --> Timer A canal 1
#define  TMRA1_CMP1             ( TMRA_BASE     + 0x10 )  //Compare Register 1
#define  TMRA1_CMP2             ( TMRA_BASE     + 0x11 )  //Compare Register 2
#define  TMRA1_CAP              ( TMRA_BASE     + 0x12 )  //Capture Register
#define  TMRA1_LOAD             ( TMRA_BASE     + 0x13 )  //Load Register
#define  TMRA1_HOLD             ( TMRA_BASE     + 0x14 )  //Hold Register
#define  TMRA1_CNTR             ( TMRA_BASE     + 0x15 )  //Counter Register
#define  TMRA1_CTRL             ( TMRA_BASE     + 0x16 )  //Control Register
#define  TMRA1_SCR              ( TMRA_BASE     + 0x17 )  //Status and Control Register
#define  TMRA1_CMPLD1           ( TMRA_BASE     + 0x18 )  //Comparator Load Register 1
#define  TMRA1_CMPLD2           ( TMRA_BASE     + 0x19 )  //Comparator Load Register 2
#define  TMRA1_COMSCR           ( TMRA_BASE     + 0x1A )  //Comparator Status and Control Register
//    --> Timer A canal 2
#define  TMRA2_CMP1             ( TMRA_BASE     + 0x20 )  //Compare Register 1
#define  TMRA2_CMP2             ( TMRA_BASE     + 0x21 )  //Compare Register 2
#define  TMRA2_CAP              ( TMRA_BASE     + 0x22 )  //Capture Register
#define  TMRA2_LOAD             ( TMRA_BASE     + 0x23 )  //Load Register
#define  TMRA2_HOLD             ( TMRA_BASE     + 0x24 )  //Hold Register
#define  TMRA2_CNTR             ( TMRA_BASE     + 0x25 )  //Counter Register
#define  TMRA2_CTRL             ( TMRA_BASE     + 0x26 )  //Control Register
#define  TMRA2_SCR              ( TMRA_BASE     + 0x27 )  //Status and Control Register
#define  TMRA2_CMPLD1           ( TMRA_BASE     + 0x28 )  //Comparator Load Register 1
#define  TMRA2_CMPLD2           ( TMRA_BASE     + 0x29 )  //Comparator Load Register 2
#define  TMRA2_COMSCR           ( TMRA_BASE     + 0x2A )  //Comparator Status and Control Register
//    --> Timer A canal 3
#define  TMRA3_CMP1             ( TMRA_BASE     + 0x30 )  //Compare Register 1
#define  TMRA3_CMP2             ( TMRA_BASE     + 0x31 )  //Compare Register 2
#define  TMRA3_CAP              ( TMRA_BASE     + 0x32 )  //Capture Register
#define  TMRA3_LOAD             ( TMRA_BASE     + 0x33 )  //Load Register
#define  TMRA3_HOLD             ( TMRA_BASE     + 0x34 )  //Hold Register
#define  TMRA3_CNTR             ( TMRA_BASE     + 0x35 )  //Counter Register
#define  TMRA3_CTRL             ( TMRA_BASE     + 0x36 )  //Control Register
#define  TMRA3_SCR              ( TMRA_BASE     + 0x37 )  //Status and Control Register
#define  TMRA3_CMPLD1           ( TMRA_BASE     + 0x38 )  //Comparator Load Register 1
#define  TMRA3_CMPLD2           ( TMRA_BASE     + 0x39 )  //Comparator Load Register 2
#define  TMRA3_COMSCR           ( TMRA_BASE     + 0x3A )  //Comparator Status and Control Register


 			/*  Registri pentru configurarea timerului B   */

//    --> Timer B canal 0
#define  TMRB0_CMP1             ( TMRB_BASE     + 0x0  )  //Compare Register 1
#define  TMRB0_CMP2             ( TMRB_BASE     + 0x1  )  //Compare Register 2
#define  TMRB0_CAP              ( TMRB_BASE     + 0x2  )  //Capture Register
#define  TMRB0_LOAD             ( TMRB_BASE     + 0x3  )  //Load Register
#define  TMRB0_HOLD             ( TMRB_BASE     + 0x4  )  //Hold Register
#define  TMRB0_CNTR             ( TMRB_BASE     + 0x5  )  //Counter Register
#define  TMRB0_CTRL             ( TMRB_BASE     + 0x6  )  //Control Register
#define  TMRB0_SCR              ( TMRB_BASE     + 0x7  )  //Status and Control Register
#define  TMRB0_CMPLD1           ( TMRB_BASE     + 0x8  )  //Comparator Load Register 1
#define  TMRB0_CMPLD2           ( TMRB_BASE     + 0x9  )  //Comparator Load Register 2
#define  TMRB0_COMSCR           ( TMRB_BASE     + 0xA  )  //Comparator Status and Control Register
//    --> Timer B canal 1
#define  TMRB1_CMP1             ( TMRB_BASE     + 0x10 )  //Compare Register 1
#define  TMRB1_CMP2             ( TMRB_BASE     + 0x11 )  //Compare Register 2
#define  TMRB1_CAP              ( TMRB_BASE     + 0x12 )  //Capture Register
#define  TMRB1_LOAD             ( TMRB_BASE     + 0x13 )  //Load Register
#define  TMRB1_HOLD             ( TMRB_BASE     + 0x14 )  //Hold Register
#define  TMRB1_CNTR             ( TMRB_BASE     + 0x15 )  //Counter Register
#define  TMRB1_CTRL             ( TMRB_BASE     + 0x16 )  //Control Register
#define  TMRB1_SCR              ( TMRB_BASE     + 0x17 )  //Status and Control Register
#define  TMRB1_CMPLD1           ( TMRB_BASE     + 0x18 )  //Comparator Load Register 1
#define  TMRB1_CMPLD2           ( TMRB_BASE     + 0x19 )  //Comparator Load Register 2
#define  TMRB1_COMSCR           ( TMRB_BASE     + 0x1A )  //Comparator Status and Control Register
//    --> Timer B canal 2
#define  TMRB2_CMP1             ( TMRB_BASE     + 0x20 )  //Compare Register 1
#define  TMRB2_CMP2             ( TMRB_BASE     + 0x21 )  //Compare Register 2
#define  TMRB2_CAP              ( TMRB_BASE     + 0x22 )  //Capture Register
#define  TMRB2_LOAD             ( TMRB_BASE     + 0x23 )  //Load Register
#define  TMRB2_HOLD             ( TMRB_BASE     + 0x24 )  //Hold Register
#define  TMRB2_CNTR             ( TMRB_BASE     + 0x25 )  //Counter Register
#define  TMRB2_CTRL             ( TMRB_BASE     + 0x26 )  //Control Register
#define  TMRB2_SCR              ( TMRB_BASE     + 0x27 )  //Status and Control Register
#define  TMRB2_CMPLD1           ( TMRB_BASE     + 0x28 )  //Comparator Load Register 1
#define  TMRB2_CMPLD2           ( TMRB_BASE     + 0x29 )  //Comparator Load Register 2
#define  TMRB2_COMSCR           ( TMRB_BASE     + 0x2A )  //Comparator Status and Control Register
//    --> Timer B canal 3
#define  TMRB3_CMP1             ( TMRB_BASE     + 0x30 )  //Compare Register 1
#define  TMRB3_CMP2             ( TMRB_BASE     + 0x31 )  //Compare Register 2
#define  TMRB3_CAP              ( TMRB_BASE     + 0x32 )  //Capture Register
#define  TMRB3_LOAD             ( TMRB_BASE     + 0x33 )  //Load Register
#define  TMRB3_HOLD             ( TMRB_BASE     + 0x34 )  //Hold Register
#define  TMRB3_CNTR             ( TMRB_BASE     + 0x35 )  //Counter Register
#define  TMRB3_CTRL             ( TMRB_BASE     + 0x36 )  //Control Register
#define  TMRB3_SCR              ( TMRB_BASE     + 0x37 )  //Status and Control Register
#define  TMRB3_CMPLD1           ( TMRB_BASE     + 0x38 )  //Comparator Load Register 1
#define  TMRB3_CMPLD2           ( TMRB_BASE     + 0x39 )  //Comparator Load Register 2
#define  TMRB3_COMSCR           ( TMRB_BASE     + 0x3A )  //Comparator Status and Control Register


 				/*  Registri pentru configurarea timerului C   */
 				
//    --> Timer C canal 0 				
#define  TMRC0_CMP1             ( TMRC_BASE     + 0x0  )  //Compare Register 1
#define  TMRC0_CMP2             ( TMRC_BASE     + 0x1  )  //Compare Register 2
#define  TMRC0_CAP              ( TMRC_BASE     + 0x2  )  //Capture Register
#define  TMRC0_LOAD             ( TMRC_BASE     + 0x3  )  //Load Register
#define  TMRC0_HOLD             ( TMRC_BASE     + 0x4  )  //Hold Register
#define  TMRC0_CNTR             ( TMRC_BASE     + 0x5  )  //Counter Register
#define  TMRC0_CTRL             ( TMRC_BASE     + 0x6  )  //Control Register
#define  TMRC0_SCR              ( TMRC_BASE     + 0x7  )  //Status and Control Register
#define  TMRC0_CMPLD1           ( TMRC_BASE     + 0x8  )  //Comparator Load Register 1
#define  TMRC0_CMPLD2           ( TMRC_BASE     + 0x9  )  //Comparator Load Register 2
#define  TMRC0_COMSCR           ( TMRC_BASE     + 0xA  )  //Comparator Status and Control Register
//    --> Timer C canal 1
#define  TMRC1_CMP1             ( TMRC_BASE     + 0x10 )  //Compare Register 1
#define  TMRC1_CMP2             ( TMRC_BASE     + 0x11 )  //Compare Register 2
#define  TMRC1_CAP              ( TMRC_BASE     + 0x12 )  //Capture Register
#define  TMRC1_LOAD             ( TMRC_BASE     + 0x13 )  //Load Register
#define  TMRC1_HOLD             ( TMRC_BASE     + 0x14 )  //Hold Register
#define  TMRC1_CNTR             ( TMRC_BASE     + 0x15 )  //Counter Register
#define  TMRC1_CTRL             ( TMRC_BASE     + 0x16 )  //Control Register
#define  TMRC1_SCR              ( TMRC_BASE     + 0x17 )  //Status and Control Register
#define  TMRC1_CMPLD1           ( TMRC_BASE     + 0x18 )  //Comparator Load Register 1
#define  TMRC1_CMPLD2           ( TMRC_BASE     + 0x19 )  //Comparator Load Register 2
#define  TMRC1_COMSCR           ( TMRC_BASE     + 0x1A )  //Comparator Status and Control Register
//    --> Timer C canal 2
#define  TMRC2_CMP1             ( TMRC_BASE     + 0x20 )  //Compare Register 1
#define  TMRC2_CMP2             ( TMRC_BASE     + 0x21 )  //Compare Register 2
#define  TMRC2_CAP              ( TMRC_BASE     + 0x22 )  //Capture Register