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📄 dingshi.lst

📁 这个是用AVR编写的程序
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__text_start:
__start:
    0041 E5CF      LDI	R28,0x5F
    0042 E0D4      LDI	R29,4
    0043 BFCD      OUT	P3D,R28
    0044 BFDE      OUT	P3E,R29
    0045 51C0      SUBI	R28,0x10
    0046 40D0      SBCI	R29,0
    0047 EA0A      LDI	R16,0xAA
    0048 8308      STD	R16,0+Y
    0049 2400      CLR	R0
    004A E6E1      LDI	R30,0x61
    004B E0F0      LDI	R31,0
    004C E010      LDI	R17,0
    004D 36E1      CPI	R30,0x61
    004E 07F1      CPC	R31,R17
    004F F011      BEQ	0x0052
    0050 9201      ST	R0,Z+
    0051 CFFB      RJMP	0x004D
    0052 8300      STD	R16,0+Z
    0053 E8E0      LDI	R30,0x80
    0054 E0F0      LDI	R31,0
    0055 E6A0      LDI	R26,0x60
    0056 E0B0      LDI	R27,0
    0057 E010      LDI	R17,0
    0058 38E1      CPI	R30,0x81
    0059 07F1      CPC	R31,R17
    005A F021      BEQ	0x005F
    005B 95C8      LPM
    005C 9631      ADIW	R30,1
    005D 920D      ST	R0,X+
    005E CFF9      RJMP	0x0058
    005F 940E00C4  CALL	_main
_exit:
    0061 CFFF      RJMP	_exit
_delay:
  x                    --> R20
  y                    --> R22
  z                    --> R16
    0062 940E010C  CALL	push_gset2
FILE: D:\chengxu\lesson7_2\lesson7_3\din0.c
(0001) #include<iom16v.h>
(0002) #include<macros.h>
(0003) #include<stdio.h>
(0004) #define uint unsigned int
(0005) #define uchar unsigned char
(0006) uchar num=0;
(0007) #pragma data:code
(0008)  const  table[]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0x77,0x7c,
(0009)                   0x39,0x5e,0x79,0x71};
(0010) #pragma interrupt_handler miao:5		  
(0011) void delay(uint z)
(0012)    {uint x,y;
(0013)     for (x=0;x<z;x++)
    0064 2744      CLR	R20
    0065 2755      CLR	R21
    0066 C00B      RJMP	0x0072
(0014) 	  for(y=0;y<1104;y++);
    0067 2766      CLR	R22
    0068 2777      CLR	R23
    0069 C002      RJMP	0x006C
    006A 5F6F      SUBI	R22,0xFF
    006B 4F7F      SBCI	R23,0xFF
    006C 3560      CPI	R22,0x50
    006D E0E4      LDI	R30,4
    006E 077E      CPC	R23,R30
    006F F3D0      BCS	0x006A
    0070 5F4F      SUBI	R20,0xFF
    0071 4F5F      SBCI	R21,0xFF
    0072 1740      CP	R20,R16
    0073 0751      CPC	R21,R17
    0074 F390      BCS	0x0067
(0015)       }
    0075 940E0110  CALL	pop_gset2
    0077 9508      RET
_show:
  y                    --> R20
  x                    --> R22
    0078 940E010C  CALL	push_gset2
    007A 2F42      MOV	R20,R18
    007B 2F60      MOV	R22,R16
(0016) 	 void show(uchar x,uchar y)
(0017)    {DDRA|=0x18;
    007C B38A      IN	R24,P1A
    007D 6188      ORI	R24,0x18
    007E BB8A      OUT	P1A,R24
(0018)     DDRB=0xff;
    007F EF8F      LDI	R24,0xFF
    0080 BB87      OUT	P17,R24
(0019)     PORTB=table[x];
    0081 E082      LDI	R24,2
    0082 9F86      MUL	R24,R22
    0083 01F0      MOVW	R30,R0
    0084 E680      LDI	R24,0x60
    0085 E090      LDI	R25,0
    0086 0FE8      ADD	R30,R24
    0087 1FF9      ADC	R31,R25
    0088 9005      LD	R0,R0
    0089 9014      LD	R1,R1
    008A 01F0      MOVW	R30,R0
    008B BBE8      OUT	P18,R30
(0020) 	PORTA|=BIT(3);
    008C 9ADB      SBI	P1B,3
(0021) 	PORTA&=~BIT(3);
    008D 98DB      CBI	P1B,3
(0022) 	PORTB=0XFF;
    008E EF8F      LDI	R24,0xFF
    008F BB88      OUT	P18,R24
(0023) 	PORTB&=~BIT(y);
    0090 E001      LDI	R16,1
    0091 2F14      MOV	R17,R20
    0092 940E0113  CALL	lsl8
    0094 2E20      MOV	R2,R16
    0095 9420      COM	R2
    0096 B238      IN	R3,P18
    0097 2032      AND	R3,R2
    0098 BA38      OUT	P18,R3
(0024) 	PORTA|=BIT(4);
    0099 9ADC      SBI	P1B,4
(0025) 	PORTA&=~BIT(4);
    009A 98DC      CBI	P1B,4
(0026) 	delay(1);}
    009B E001      LDI	R16,1
    009C E010      LDI	R17,0
    009D DFC4      RCALL	_delay
    009E 940E0110  CALL	pop_gset2
    00A0 9508      RET
(0027)  /* void show(uchar x,uchar y)
(0028)    {DDRA|=0X18;
(0029)     DDRB=0XFF;
(0030) 	PORTB=table[x];
(0031) 	PORTA|=BIT(3);
(0032) 	PORTA&=~BIT(3);
(0033) 	PORTB=0XFF;
(0034) 	PORTB&=~BIT(y);
(0035) 	PORTA|=BIT(4);
(0036) 	PORTA&=~BIT(4);
(0037) 	delay(1);
(0038)    }*/	
(0039)    void init() //定时器0的初始化
(0040)     {TCNT0=0X01;
_init:
    00A1 E081      LDI	R24,1
    00A2 BF82      OUT	P32,R24
(0041) 	 TCCR0=0x05;
    00A3 E085      LDI	R24,5
    00A4 BF83      OUT	P33,R24
(0042) 	 TIMSK|=BIT(2);
    00A5 B789      IN	R24,P39
    00A6 6084      ORI	R24,4
    00A7 BF89      OUT	P39,R24
(0043) 	 SREG|=BIT(7);
    00A8 9478      BSET	7
(0044) 	 }
    00A9 9508      RET
_miao:
    00AA 922A      ST	R2,-Y
    00AB 938A      ST	R24,-Y
    00AC 939A      ST	R25,-Y
    00AD B62F      IN	R2,P3F
    00AE 922A      ST	R2,-Y
(0045) 	 
(0046) 	  
(0047) 	/*   void init() //定时器2的初始化
(0048)     {TCNT2=0X01;
(0049) 	 TCCR2=0x05;
(0050) 	 TIMSK|=BIT(6);
(0051) 	 SREG|=BIT(7);
(0052) 	 }
(0053) 	  void miao() //中断函数2
(0054) 	  {if(num==1000)
(0055) 	    {num=0;}
(0056) 	   else num++;
(0057) 	   TCNT2=0X01;
(0058) 	  }*/
(0059) 	 void miao() //中断函数0
(0060) 	  {if(num==1000)
    00AF 91800060  LDS	R24,0x60
    00B1 3E88      CPI	R24,0xE8
    00B2 F421      BNE	0x00B7
(0061) 	    {num=0;}
    00B3 2422      CLR	R2
    00B4 92200060  STS	R2,0x60
    00B6 C005      RJMP	0x00BC
(0062) 	   else num++;
    00B7 91800060  LDS	R24,0x60
    00B9 5F8F      SUBI	R24,0xFF
    00BA 93800060  STS	R24,0x60
(0063) 	   TCNT0=0X01;
    00BC E081      LDI	R24,1
    00BD BF82      OUT	P32,R24
(0064) 	  }
    00BE 9029      LD	R2,Y+
    00BF BE2F      OUT	P3F,R2
    00C0 9199      LD	R25,Y+
    00C1 9189      LD	R24,Y+
    00C2 9029      LD	R2,Y+
    00C3 9518      RETI
(0065) 	  			  
(0066)   void main(void)
(0067)     {uchar fen=0;
_main:
  fen                  --> R20
    00C4 2744      CLR	R20
(0068) 	init();
    00C5 DFDB      RCALL	_init
    00C6 C018      RJMP	0x00DF
(0069) 	while(1)
(0070)       {
(0071) 	  if(num==1000)
    00C7 91800060  LDS	R24,0x60
    00C9 3E88      CPI	R24,0xE8
    00CA F441      BNE	0x00D3
(0072) 	  {num=0;
    00CB 2422      CLR	R2
    00CC 92200060  STS	R2,0x60
(0073) 	   if(fen==59)
    00CE 334B      CPI	R20,0x3B
    00CF F411      BNE	0x00D2
(0074) 	   {fen=0;
    00D0 2744      CLR	R20
(0075) 	   }
    00D1 C001      RJMP	0x00D3
(0076) 	   else fen++;
    00D2 9543      INC	R20
(0077) 	   }
(0078) 	 show(fen/10,0);
    00D3 2722      CLR	R18
    00D4 E01A      LDI	R17,0xA
    00D5 2F04      MOV	R16,R20
    00D6 940E00E3  CALL	div8u
    00D8 DF9F      RCALL	_show
(0079) 	 show(fen%10,1);
    00D9 E021      LDI	R18,1
    00DA E01A      LDI	R17,0xA
    00DB 2F04      MOV	R16,R20
    00DC 940E00E1  CALL	mod8u
    00DE DF99      RCALL	_show
    00DF CFE7      RJMP	0x00C7
(0080) 	  }
(0081) }	FILE: <library>
    00E0 9508      RET
mod8u:
    00E1 9468      BSET	6
    00E2 C001      RJMP	xdiv8u
div8u:
    00E3 94E8      BCLR	6
xdiv8u:
    00E4 932A      ST	R18,-Y
    00E5 92FA      ST	R15,-Y
    00E6 24FF      CLR	R15
    00E7 E028      LDI	R18,0x8
    00E8 0F00      LSL	R16
    00E9 1CFF      ROL	R15
    00EA 16F1      CP	R15,R17
    00EB F010      BCS	0x00EE
    00EC 1AF1      SUB	R15,R17
    00ED 9503      INC	R16
    00EE 952A      DEC	R18
    00EF F7C1      BNE	0x00E8
    00F0 F40E      BRTC	0x00F2
    00F1 2D0F      MOV	R16,R15
    00F2 90F9      LD	R15,Y+
    00F3 9129      LD	R18,Y+
    00F4 9508      RET
push_gset1:
    00F5 935A      ST	R21,-Y
    00F6 934A      ST	R20,-Y
    00F7 9508      RET
pop_gset1:
    00F8 E0E1      LDI	R30,1
pop:
    00F9 9149      LD	R20,Y+
    00FA 9159      LD	R21,Y+
    00FB FDE0      SBRC	R30,0
    00FC 9508      RET
    00FD 9169      LD	R22,Y+
    00FE 9179      LD	R23,Y+
    00FF FDE1      SBRC	R30,1
    0100 9508      RET
    0101 90A9      LD	R10,Y+
    0102 90B9      LD	R11,Y+
    0103 FDE2      SBRC	R30,2
    0104 9508      RET
    0105 90C9      LD	R12,Y+
    0106 90D9      LD	R13,Y+
    0107 FDE3      SBRC	R30,3
    0108 9508      RET
    0109 90E9      LD	R14,Y+
    010A 90F9      LD	R15,Y+
    010B 9508      RET
push_gset2:
    010C 937A      ST	R23,-Y
    010D 936A      ST	R22,-Y
    010E 940C00F5  JMP	push_gset1
pop_gset2:
    0110 E0E2      LDI	R30,2
    0111 940C00F9  JMP	pop
lsl8:
    0113 2311      TST	R17
    0114 F019      BEQ	0x0118
    0115 0F00      LSL	R16
    0116 951A      DEC	R17
    0117 CFFB      RJMP	lsl8
    0118 9508      RET

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