📄 hardware.lst
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// ...
// call F_SP_SACM_A2000_Init_ : S480/S240/MS01 is same
// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
0000C33F 40 92 r1=0x0000; // 24MHz, Fcpu=Fosc
0000C340 19 D3 13 70 [P_SystemClock]=r1 // Frequency 20MHz
0000C342 70 92 r1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C343 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
0000C345 09 93 00 FD r1 = 0xfd00 // 16K
0000C347 19 D3 0A 70 [P_TimerA_Data] = r1
0000C349 09 93 A8 00 r1 = 0x00A8 // Set the DAC Ctrl
0000C34B 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C34D 09 93 FF FF r1 = 0xffff
0000C34F 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
0000C351 40 92 r1 =0x0000 //
// r1 = [R_InterruptStatus] //
0000C352 11 93 2D 70 r1 = [P_INT_Mask]
0000C354 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C356 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C358 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
0000C359 40 92 r1 = 0x0000 // 24MHz Fosc
0000C35A 19 D3 13 70 [P_SystemClock]=r1 // Initial System Clock
0000C35C 70 92 r1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C35D 19 D3 0B 70 [P_TimerA_Ctrl]=r1 // Initial Timer A
//R1 = 0xfd00 // 16K
0000C35F 09 93 ED FC r1 = 0xfced // 15.625K
0000C361 19 D3 0A 70 [P_TimerA_Data]=r1
0000C363 09 93 A8 00 r1 = 0x00A8 //
0000C365 19 D3 2A 70 [P_DAC_Ctrl] = r1 //
0000C367 09 93 FF FF r1 = 0xffff
0000C369 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
// R1 = [R_InterruptStatus] //
0000C36B 11 93 2D 70 r1 = [P_INT_Mask]
0000C36D 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
// [R_InterruptStatus] = r1 //
0000C36F 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C371 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
0000C372 60 92 r1=0x0020;
0000C373 19 D3 13 70 [P_SystemClock]=r1
0000C375 09 93 A8 00 r1 = 0x00A8; //
0000C377 19 D3 2A 70 [P_DAC_Ctrl]= r1
0000C379 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C37A 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000C37C 09 93 00 FE r1 = 0xfe00; // 24K
0000C37E 19 D3 0A 70 [P_TimerA_Data] = r1;
0000C380 09 93 FF FF r1 = 0xffff
0000C382 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
// r1 = [R_InterruptStatus] //
0000C384 11 93 2D 70 r1 = [P_INT_Mask]
0000C386 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
// [R_InterruptStatus] = r1 //
0000C388 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C38A 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
0000C38B 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000C38C 19 D3 13 70 [P_SystemClock] = r1; // Initial System Clock
0000C38E 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C38F 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
//R1 = 0x0003 // 8K
0000C391 40 92 r1 = 0x0000 // Fosc/2
0000C392 19 D3 0D 70 [P_TimerB_Ctrl] = r1; // Initial Timer B -> 8192
//R1 = 0xFFFF
0000C394 09 93 00 FA r1 = 0xFA00 // Any time for ADPCM channel 0,1
0000C396 19 D3 0C 70 [P_TimerB_Data] = r1 // 8K sample rate
0000C398 09 93 FF FF r1 = 0xffff
0000C39A 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
0000C39C 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
0000C39D 46 92 r1 = 0x0006
0000C39E 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C3A0 09 93 00 FE r1 = 0xFE00
0000C3A2 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
0000C3A4 11 93 2D 70 r1 = [P_INT_Mask]
0000C3A6 09 A3 10 84 r1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C3A8 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C3AA 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
0000C3AB 09 93 A8 00 r1 = 0x00A8
0000C3AD 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C3AF 09 93 00 FE r1 = 0xFE00
0000C3B1 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
0000C3B3 11 93 2D 70 r1 = [P_INT_Mask]
0000C3B5 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C3B7 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C3B9 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
0000C3BA 09 93 A8 00 r1 = 0x00A8
0000C3BC 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C3BE 09 93 9A FD r1 = 0xFD9A
0000C3C0 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
0000C3C2 11 93 2D 70 r1 = [P_INT_Mask]
0000C3C4 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C3C6 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C3C8 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
0000C3C9 09 93 A8 00 r1 = 0x00A8
0000C3CB 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C3CD 09 93 00 FD r1 = 0xFD00
0000C3CF 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
0000C3D1 11 93 2D 70 r1 = [P_INT_Mask]
// r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C3D3 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C3D5 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
0000C3D6 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000C3D7 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
0000C3D9 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C3DA 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000C3DC 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
0000C3DE 19 D3 0A 70 [P_TimerA_Data] = r1;
0000C3E0 75 92 r1 = 0x0035; // ADINI should be open (107)
0000C3E1 19 D3 15 70 [P_ADC_Ctrl] = r1;
0000C3E3 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
0000C3E5 19 D3 2A 70 [P_DAC_Ctrl] = r1;
0000C3E7 09 93 FF FF r1 = 0xffff;
0000C3E9 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
// r1 = [R_InterruptStatus] //
0000C3EB 11 93 2D 70 r1 = [P_INT_Mask]
0000C3ED 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
// [R_InterruptStatus] = r1 //
0000C3EF 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C3F1 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
0000C3F2 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
0000C3F3 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
0000C3F5 09 93 00 FE r1=0xfe00; //24K @ 24.576MHz
0000C3F7 19 D3 0A 70 [P_TimerA_Data] = r1
0000C3F9 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
0000C3FA 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
0000C3FB 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
0000C3FD 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
0000C3FF 19 D3 0A 70 [P_TimerA_Data] = r1;
0000C401 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
0000C402 90 D4 push r1,r2 to [sp]
0000C403 11 93 17 70 r1=[P_DAC1]
0000C405 09 B3 C0 FF r1 &= ~0x003f
0000C407 09 43 00 80 cmp r1,0x8000
0000C409 0E 0E jb L_RU_NormalUp
0000C40A 19 5E je L_RU_End
L_RU_DownLoop:
0000C40B 40 F0 6E C4 call F_Delay
0000C40D 41 94 r2 = 0x0001
0000C40E 1A D5 12 70 [P_Watchdog_Clear] = r2
0000C410 09 23 40 00 r1 -= 0x40
0000C412 19 D3 17 70 [P_DAC1] = r1
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