📄 hardware.lst
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// ...
// call F_SP_SACM_A2000_Init_ : S480/S240/MS01 is same
// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
0000C52C 40 92 r1=0x0000; // 24MHz, Fcpu=Fosc
0000C52D 19 D3 13 70 [P_SystemClock]=r1 // Frequency 20MHz
0000C52F 70 92 r1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C530 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
0000C532 09 93 00 FD r1 = 0xfd00 // 16K
0000C534 19 D3 0A 70 [P_TimerA_Data] = r1
0000C536 09 93 A8 00 r1 = 0x00A8 // Set the DAC Ctrl
0000C538 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C53A 09 93 FF FF r1 = 0xffff
0000C53C 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
0000C53E 40 92 r1 =0x0000 //
// r1 = [R_InterruptStatus] //
0000C53F 11 93 2D 70 r1 = [P_INT_Mask]
0000C541 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C543 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C545 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
0000C546 40 92 r1 = 0x0000 // 24MHz Fosc
0000C547 19 D3 13 70 [P_SystemClock]=r1 // Initial System Clock
0000C549 70 92 r1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C54A 19 D3 0B 70 [P_TimerA_Ctrl]=r1 // Initial Timer A
//R1 = 0xfd00 // 16K
0000C54C 09 93 ED FC r1 = 0xfced // 15.625K
0000C54E 19 D3 0A 70 [P_TimerA_Data]=r1
0000C550 09 93 A8 00 r1 = 0x00A8 //
0000C552 19 D3 2A 70 [P_DAC_Ctrl] = r1 //
0000C554 09 93 FF FF r1 = 0xffff
0000C556 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
// R1 = [R_InterruptStatus] //
0000C558 11 93 2D 70 r1 = [P_INT_Mask]
0000C55A 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
// [R_InterruptStatus] = r1 //
0000C55C 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C55E 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
0000C55F 60 92 r1=0x0020;
0000C560 19 D3 13 70 [P_SystemClock]=r1
0000C562 09 93 A8 00 r1 = 0x00A8; //
0000C564 19 D3 2A 70 [P_DAC_Ctrl]= r1
0000C566 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C567 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000C569 09 93 00 FE r1 = 0xfe00; // 24K
0000C56B 19 D3 0A 70 [P_TimerA_Data] = r1;
0000C56D 09 93 FF FF r1 = 0xffff
0000C56F 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
// r1 = [R_InterruptStatus] //
0000C571 11 93 2D 70 r1 = [P_INT_Mask]
0000C573 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
// [R_InterruptStatus] = r1 //
0000C575 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C577 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
0000C578 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000C579 19 D3 13 70 [P_SystemClock] = r1; // Initial System Clock
0000C57B 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C57C 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
//R1 = 0x0003 // 8K
0000C57E 40 92 r1 = 0x0000 // Fosc/2
0000C57F 19 D3 0D 70 [P_TimerB_Ctrl] = r1; // Initial Timer B -> 8192
//R1 = 0xFFFF
0000C581 09 93 00 FA r1 = 0xFA00 // Any time for ADPCM channel 0,1
0000C583 19 D3 0C 70 [P_TimerB_Data] = r1 // 8K sample rate
0000C585 09 93 FF FF r1 = 0xffff
0000C587 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
0000C589 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
0000C58A 46 92 r1 = 0x0006
0000C58B 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C58D 09 93 00 FE r1 = 0xFE00
0000C58F 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
0000C591 11 93 2D 70 r1 = [P_INT_Mask]
0000C593 09 A3 10 84 r1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C595 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C597 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
0000C598 09 93 A8 00 r1 = 0x00A8
0000C59A 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C59C 09 93 00 FE r1 = 0xFE00
0000C59E 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
0000C5A0 11 93 2D 70 r1 = [P_INT_Mask]
0000C5A2 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C5A4 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C5A6 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
0000C5A7 09 93 A8 00 r1 = 0x00A8
0000C5A9 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C5AB 09 93 9A FD r1 = 0xFD9A
0000C5AD 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
0000C5AF 11 93 2D 70 r1 = [P_INT_Mask]
0000C5B1 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C5B3 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C5B5 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
0000C5B6 09 93 A8 00 r1 = 0x00A8
0000C5B8 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000C5BA 09 93 00 FD r1 = 0xFD00
0000C5BC 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
0000C5BE 11 93 2D 70 r1 = [P_INT_Mask]
// r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
// [R_InterruptStatus] = r1 //
0000C5C0 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C5C2 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
0000C5C3 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000C5C4 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
0000C5C6 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000C5C7 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000C5C9 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
0000C5CB 19 D3 0A 70 [P_TimerA_Data] = r1;
0000C5CD 75 92 r1 = 0x0035; // ADINI should be open (107)
0000C5CE 19 D3 15 70 [P_ADC_Ctrl] = r1;
0000C5D0 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
0000C5D2 19 D3 2A 70 [P_DAC_Ctrl] = r1;
0000C5D4 09 93 FF FF r1 = 0xffff;
0000C5D6 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
// r1 = [R_InterruptStatus] //
0000C5D8 11 93 2D 70 r1 = [P_INT_Mask]
0000C5DA 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
// [R_InterruptStatus] = r1 //
0000C5DC 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000C5DE 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
0000C5DF 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
0000C5E0 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
0000C5E2 09 93 00 FE r1=0xfe00; //24K @ 24.576MHz
0000C5E4 19 D3 0A 70 [P_TimerA_Data] = r1
0000C5E6 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
0000C5E7 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
0000C5E8 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
0000C5EA 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
0000C5EC 19 D3 0A 70 [P_TimerA_Data] = r1;
0000C5EE 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
0000C5EF 90 D4 push r1,r2 to [sp]
0000C5F0 11 93 17 70 r1=[P_DAC1]
0000C5F2 09 B3 C0 FF r1 &= ~0x003f
0000C5F4 09 43 00 80 cmp r1,0x8000
0000C5F6 0E 0E jb L_RU_NormalUp
0000C5F7 19 5E je L_RU_End
L_RU_DownLoop:
0000C5F8 40 F0 5B C6 call F_Delay
0000C5FA 41 94 r2 = 0x0001
0000C5FB 1A D5 12 70 [P_Watchdog_Clear] = r2
0000C5FD 09 23 40 00 r1 -= 0x40
0000C5FF 19 D3 17 70 [P_DAC1] = r1
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