universe.h

universeII驱动

#define DMA_VON_256BYTES            0x00100000
#define DMA_VON_512BYTES            0x00200000
#define DMA_VON_1024BYTES           0x00300000
#define DMA_VON_2048BYTES           0x00400000
#define DMA_VON_4096BYTES           0x00500000
#define DMA_VON_8192BYTES           0x00600000
#define DMA_VON_16384BYTES          0x00700000
#define DMA_VOFF_0US                0x00000000
#define DMA_VOFF_16US               0x00010000
#define DMA_VOFF_32US               0x00020000
#define DMA_VOFF_64US               0x00030000
#define DMA_VOFF_128US              0x00040000
#define DMA_VOFF_256US              0x00050000
#define DMA_VOFF_512US              0x00060000
#define DMA_VOFF_1024US             0x00070000
#define DMA_VOFF_2US                0x00080000
#define DMA_VOFF_4US                0x00090000
#define DMA_VOFF_8US                0x000a0000
#define DMA_ACTIVE                  0x00008000
#define DMA_STOPPED                 0x00004000
#define DMA_HALTED                  0x00002000
#define DMA_DONE                    0x00000800
#define DMA_LERR                    0x00000400
#define DMA_VERR                    0x00000200
#define DMA_PERR                    0x00000100
#define DMA_INT_STOP                0x00000040
#define DMA_INT_HALT                0x00000020
#define DMA_INT_DONE                0x00000008
#define DMA_INT_LERR                0x00000004
#define DMA_INT_VERR                0x00000002
#define DMA_INT_PERR                0x00000001

  /* 
   * Fortunately, none of the needed bits overlap, so dma flags can just be the
   * & of the valid flags for both of these registers
   */
#define DMA_VALID_DCTL_FLAGS        0x80000180
#define DMA_VALID_DGCS_FLAGS        0x687f0000
#define DMA_VALID_USER_FLAGS        0x707f0180
#define DMA_BLOCKING                0x10000000  /* Or this to flags to make a
                                                   blocking DMA transfer call */
#define DMA_DEFAULT_FLAGS           DMA_BLOCKING

  /* 
   * VMIC PCI definitions
   */
#define VMIC_VENDOR_ID              0x114a
#define VMIC_PLX_DEVICE_ID          0x0001
#define VMIC_FPGA_DEVICE_ID1        0x0004
#define VMIC_FPGA_DEVICE_ID2        0x0005
#define VMIC_PLX_BASE_ADDR_REG      0x18
#define PLX_BASE_ADDR_REG           0x10
#define VMIC_FPGA_BASE_ADDR_REG     0x10

  /* 
   * Register offsets for ISA
   */
#define VMIC_ISA_BASE               0xd8000
#define ISA_COMM_OFFSET             0x0e
#define ISA_VBAR_OFFSET             0x10
#define ISA_VBAMR_OFFSET            0x14
#define ISA_ID_OFFSET               0x16

  /* 
   * Register offsets for PLX device
   */
#define PLX_COMM_OFFSET             0x00
#define PLX_B_INT_STATUS_OFFSET     0x04
#define PLX_B_INT_MASK_OFFSET       0x08
#define PLX_B_ADDRESS_OFFSET        0x0C
#define PLX_CSR_OFFSET              0x68

  /*
   * Register offset for FPGA device
   */
#define FPGA_COMM_OFFSET            0x00
#define FPGA_VBAMR_OFFSET           0x04
#define FPGA_VBAR_OFFSET            0x08

  /* 
   * Bit values common to PLX, FPGA, and ISA registers
   */
#define MEC                         0x00000001
#define SEC                         0x00000002
#define ABLE                        0x00000004
#define BTO_EN                      0x00000008
#define BTO_16US                    0x00000000
#define BTO_64US                    0x00000010
#define BTO_256US                   0x00000020
#define BTO_1MS                     0x00000030
#define VME_EN                      0x00000800
#define VME_DIS                     0x0000F7FF

  /* 
   * ISA register specific bit values
   */
#define BERRI_ISA                   0x00000040
#define BERRST_ISA                  0x00000080
#define WTDSYS_ISA                  0x00000100

  /* 
   * PLX specific bit values
   */
#define BERRIM_INTA_PLX             0x00000000
#define BERRIM_NMI_PLX              0x00000040
#define MB_M0_EN_PLX                0x00000080
#define BERR_S_PLX                  0x00000001
#define BERR_M_PLX                  0x0001
#define PLX_INTR_ENABLE             0x00000800

  /* 
   * FPGA register specific bit values
   */
#define BERRI_FPGA                  0x00000040
#define BERRST_FPGA                 0x00000080
#define WTDSYS_FPGA                 0x00000100


/* Redefine old enumerated types that had names that confict with the new
   enumerated types
 */
#define V_A32UMB                    VME_A32UMB
#define V_A32UD                     VME_A32UD
#define V_A32UP                     VME_A32UP
#define V_A32UB                     VME_A32UB
#define V_A32SMB                    VME_A32SMB
#define V_A32SD                     VME_A32SD
#define V_A32SP                     VME_A32SP
#define V_A32SB                     VME_A32SB
#define V_A16UD                     VME_A16U
#define V_A16SD                     VME_A16S
#define V_A24UMB                    VME_A24UMB
#define V_A24UD                     VME_A24UD
#define V_A24UP                     VME_A24UP
#define V_A24UB                     VME_A24UB
#define V_A24SMB                    VME_A24SMB
#define V_A24SD                     VME_A24SD
#define V_A24SP                     VME_A24SP
#define V_A24SB                     VME_A24SB

#define V_D8                        VME_D8
#define V_D16                       VME_D16
#define V_D32                       VME_D32
#define V_D64                       VME_D64

#define V_DEMAND                    VME_DEMAND
#define V_FAIR                      VME_FAIR

#define V_RWD                       VME_RELEASE_ON_REQUEST
#define V_ROR                       VME_RELEASE_WHEN_DONE

  typedef enum
  {
    V_POSTED_WRITE_CNT_0 = 0,   /* Early release of BBSY */
    V_POSTED_WRITE_CNT_128 = 128,       /* 128 byte posted write transfer count */
    V_POSTED_WRITE_CNT_512 = 512,       /* 512 byte posted write transfer count */
    V_POSTED_WRITE_CNT_1024 = 1024,     /* 1024 byte posted write transfer count */
    V_POSTED_WRITE_CNT_2048 = 2048,     /* 2048 byte posted write transfer count */
    V_POSTED_WRITE_CNT_4096 = 4096      /* 4096 byte posted write transfer count */
  }
  vme_posted_write_count_t;

  typedef enum
  {
    V_BR0 = 0,                  /* VMEbus request level 0 */
    V_BR1 = 1,                  /* VMEbus request level 1 */
    V_BR2 = 2,                  /* VMEbus request level 2 */
    V_BR3 = 3                   /* VMEbus request level 3 */
  }
  vme_bus_request_level_t;

  typedef enum
  {
    V_RELEASE_BUS,              /* VMEbus release */
    V_ACQ_AND_HOLD_BUS          /* VMEbus aquire and hold */
  }
  vme_vown_t;

  typedef enum
  {
    V_BTO_DISABLE = 0,          /* VMEbus timeout disabled */
    V_BTO_16uS = 16,            /* VMEbus 16us timeout */
    V_BTO_32uS = 32,            /* VMEbus 32us timeout */
    V_BTO_64uS = 64,            /* VMEbus 64us timeout */
    V_BTO_128uS = 128,          /* VMEbus 128us timeout */
    V_BTO_256uS = 256,          /* VMEbus 256us timeout */
    V_BTO_512uS = 512,          /* VMEbus 512us timeout */
    V_BTO_1024uS = 1024         /* VMEbus 1024us timeout */
  }
  vme_bus_timeout_t;

  typedef enum
  {
    V_ARB_RNDRBN,               /* VMEbus round-robin mode arbitration */
    V_ARB_PRIORITY              /* VMEbus priority mode arbitration */
  }
  vme_bus_arbitration_mode_t;

  typedef enum
  {
    V_ARB_TO_DISABLE = 0,       /* VMEbus arbitration timeout disabled */
    V_ARB_TO_16uS = 16,         /* VMEbus 16us arbitration timeout */
    V_ARB_TO_256uS = 256        /* VMEbus 256us arbitration timeout */
  }
  vme_bus_arbitration_timeout_t;

  typedef enum
  {
    V_ENDIAN_CONVERSION_OFF = 0,        /* VMEbus hardware endian conversion off */
    V_ENDIAN_CONVERSION_ON = 1  /* VMEbus hardware endian conversion on */
  }
  vme_endian_conversion_t;

  typedef enum
  {
    VOWN_INT_LVL = 0,           /* VOWN interrupt */
    VME_INT_LVL1 = 1,           /* VMEbus interrupt level 1 */
    VME_INT_LVL2 = 2,           /* VMEbus interrupt level 2 */
    VME_INT_LVL3 = 3,           /* VMEbus interrupt level 3 */
    VME_INT_LVL4 = 4,           /* VMEbus interrupt level 4 */
    VME_INT_LVL5 = 5,           /* VMEbus interrupt level 5 */
    VME_INT_LVL6 = 6,           /* VMEbus interrupt level 6 */
    VME_INT_LVL7 = 7,           /* VMEbus interrupt level 7 */
    DMA_INT_LVL = 8,            /* DMA interrupt */
    PCI_BERR_LVL = 9,           /* PCI error interrupt */
    VME_BERR_LVL = 10,          /* VMEbus error interrupt */
    IACK_INT_LVL = 12,          /* Software interrupt acknowledge interrupt */
    SW_INT_LVL = 13,            /* Software interrupt */
    SYSFAIL_INT_LVL = 14,       /* System fail interrupt */
    ACFAIL_INT_LVL = 15,        /* Power fail interrupt */
    MB_INT_LVL1 = 16,           /* Mailbox interrupt level 1 */
    MB_INT_LVL2 = 17,           /* Mailbox interrupt level 2 */
    MB_INT_LVL3 = 18,           /* Mailbox interrupt level 3 */
    MB_INT_LVL4 = 19,           /* Mailbox interrupt level 4 */
    LM_INT_LVL1 = 20,           /* Location monitor interrupt level 1 */
    LM_INT_LVL2 = 21,           /* Location monitor interrupt level 2 */
    LM_INT_LVL3 = 22,           /* Location monitor interrupt level 3 */
    LM_INT_LVL4 = 23            /* Location monitor interrupt level 4 */
  }
  vme_intr_lvl_t;
#define MAX_INT_LVL      LM_INT_LVL4

  /* 
   * Interrupt vectors 
   */
#define MAX_AUX_VECTORS  24     /* Max Auxiliary vectors. */
#define MAX_INT_VECTORS  256    /* Max number of IRQ vectors. */
#define MAX_INT_LEVELS   7      /* Max Interrupt levels [1-7] */

  /* 
   * Total number of interrupt handlers including all VMEbus interrupt
   * levels and vectors plus the other interrupt levels 
   */
#define MAX_HANDLERS  ( ( MAX_INT_VECTORS * MAX_INT_LEVELS ) + MAX_AUX_VECTORS)

  /* 
   * These vectors sit on top of the VMEbus interrupt vectors in a single
   * dimensional array 
   */
#define VOWN_VECTOR          ( MAX_INT_LEVELS * MAX_INT_VECTORS )
#define DMA_VECTOR           ( VOWN_VECTOR + DMA_INT_LVL )
#define PCI_BERR_VECTOR      ( VOWN_VECTOR + PCI_BERR_LVL )
#define VME_BERR_VECTOR      ( VOWN_VECTOR + VME_BERR_LVL )
#define IACK_VECTOR          ( VOWN_VECTOR + IACK_INT_LVL )
#define SW_VECTOR            ( VOWN_VECTOR + SW_INT_LVL )
#define SYSFAIL_VECTOR       ( VOWN_VECTOR + SYSFAIL_INT_LVL )
#define ACFAIL_VECTOR        ( VOWN_VECTOR + ACFAIL_INT_LVL )
#define MBOX_VECTOR( num )   ( VOWN_VECTOR + MB_INT_LVL1 + ( num ) )
#define LM_VECTOR( num )     ( VOWN_VECTOR + LM_INT_LVL1 + ( num ) )

  /*
   * Computation to get interrupt table index
   */
#define INTR_TABLE_INDEX( _lvl, _vec ) \
( ( ( VME_INT_LVL1 <= ( _lvl ) ) && ( VME_INT_LVL7 >= ( _lvl ) ) ) ? \
( ( ( _lvl ) - 1 ) * MAX_INT_VECTORS ) + ( _vec ) : VOWN_VECTOR + ( _lvl ) )

#define INDEX_TO_LVL_VEC( _idx, _lvl, _vec ) \
if ( VOWN_VECTOR <= ( _idx ) ) \
{ ( _lvl ) = ( _idx ) - VOWN_VECTOR; ( _vec ) = 0; } \
else \
{ ( _lvl ) = ( ( _idx ) / MAX_INT_VECTORS ) + 1; \
( _vec ) = ( _idx ) % MAX_INT_VECTORS; }


#ifdef __cplusplus
}

#endif                          /* __cplusplus */

#endif                          /* __LEGACY_UNIVERSE_H */