universe.h

universeII驱动

/*
===============================================================================
                            COPYRIGHT NOTICE

    Copyright (C) 2002 VMIC
    International Copyright Secured.  All Rights Reserved.

-------------------------------------------------------------------------------

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

   o Redistributions of source code must retain the above copyright notice, this
     list of conditions and the following disclaimer.
   o Redistributions in binary form must reproduce the above copyright notice,
     this list of conditions and the following disclaimer in the documentation
     and/or other materials provided with the distribution.
   o Neither the name of VMIC nor the names of its contributors may be used to
     endorse or promote products derived from this software without specific
     prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

===============================================================================
*/


#ifndef __LEGACY_UNIVERSE_H
#define __LEGACY_UNIVERSE_H

#ifdef __cplusplus
extern "C"
{

#endif                          /* __cplusplus */


#warning Use of the header file vmic/universe.h has been deprecated in favor of the header file vme/universe.h


#include <vme/universe.h>
#include <vme/vme.h>


#ifndef PAGESIZE
#define PAGESIZE                   0x1000
#endif

  /* 
   *  Universe PCI device definitions 
   */
#define UNIVERSE_VENDOR_ID          0x10e3
#define UNIVERSE_DEVICE_ID          0x0

#define UNIVERSE_BASE_ADDR_REG      0x10
#define UNIVERSE_ALT_BASE_ADDR_REG  0x14

  /* 
   *  VME window definitions 
   */
#define MAX_VME_MASTER_WINDOWS      8
#define MAX_VME_SLAVE_WINDOWS       8

  /* 
   *  Universe device registers 
   */
#define PCI_CSR    0x4          /* PCI configuration space control and status */
  /* PCI target image (x) control register */
#define LSI_CTL(x) 0x100 + ((x) * 0x14) + (((x) >= 4) ? 0x50 : 0)
#define LSI_BS(x)  LSI_CTL(x) + 0x4     /* PCI target image (x) base address
                                           register */
#define LSI_BD(x)  LSI_CTL(x) + 0x8     /* PCI target image (x) bound address
                                           register */
#define LSI_TO(x)  LSI_CTL(x) + 0xC     /* PCI target image (x) translation
                                           offset register */
#define SLSI       0x188        /* Special PCI target image register */
#define DCTL       0x200        /* DMA transfer control register */
#define DTBC       0x204        /* DMA transfer byte count register */
#define DLA        0x208        /* DMA PCI bus address register */
#define DVA        0x210        /* DMA VME address register */
#define DCPP       0x218        /* DMA command packet pointer */
#define DGCS       0x220        /* DMA general control and status register */
#define D_LLUE     0x224        /* DMA linked list update enable register */
#define LINT_EN    0x300        /* PCI interrupt enable register */
#define LINT_STAT  0x304        /* PCI interrupt status register */
#define LINT_MAP0  0x308        /* PCI interrupt map 0 register */
#define LINT_MAP1  0x30c        /* PCI interrupt map 1 register */
#define LINT_MAP2  0x340        /* PCI interrupt map 2 register */
#define VINT_EN    0x310        /* VME interrupt enable register */
#define VINT_STAT  0x314        /* VME interrupt status register */
#define VINT_MAP0  0x318        /* VME interrupt map 0 register */
#define VINT_MAP1  0x31c        /* VME interrupt map 1 register */
#define VINT_MAP2  0x344        /* VME interrupt map 1 register */
#define STATID_OUT 0x320        /* Interrupt status/id out register */
#define STATID_IN(x)  (0x324 + (((x) - 1) * 4 ))        /* VIRQ(x) status/id in
                                                           register */
#define MBOX(x)    0x348 + ((x) * 4)    /* Mailbox (x) register */
#define SEMA(x)    0x358 + ((x) * 4)    /* Semaphore (x) register */
#define MAST_CTL   0x400        /* Master control register */
#define MISC_CTL   0x404        /* Miscellaneous control register */
  /* Slave image (x) control register */
#define VSI_CTL(x) 0xF00 + ((x) * 0x14) + ((x >= 4) ? 0x40 : 0)
#define VSI_BS(x)  VSI_CTL(x) + 0x4     /* Slave image (x) base address
                                           register */
#define VSI_BD(x)  VSI_CTL(x) + 0x8     /* Slave image (x) bound address
                                           register */
#define VSI_TO(x)  VSI_CTL(x) + 0xC     /* Slave image (x) translation offset
                                           register */
#define LM_CTL     0xF64        /* Location monitor control register */
#define LM_BS      0xF68        /* Location monitor base address register */
#define VRAI_CTL   0xF70        /* VME register access image control register */
#define VRAI_BS    0xF74        /* VME register access image base address
                                   register */
#define VAMERR     0xF88        /* VMEbus AM code error log */
#define VAERR      0xF8C        /* VMEbus address error log */

  /* 
   *  PCI Configuration space control and status register 
   */
#define PCI_MS_EN                   0x00000004
#define PCI_MS_DIS                  ~MS_EN      /* and'd */

  /*
   * Common image values
   */
#define IMAGE_EN                    0x80000000
#define IMAGE_DIS                   ~IMAGE_EN   /* and'd */
#define PWEN                        0x40000000

  /* 
   *  PCI target image registers
   */
#define TRGT_VDW_64                 0x00C00000
#define TRGT_VDW_32                 0x00800000
#define TRGT_VDW_16                 0x00400000
#define TRGT_VDW_8                  0x00000000
#define TRGT_VAS_USER2              0x00070000
#define TRGT_VAS_USER1              0x00060000
#define TRGT_VAS_A32                0x00020000
#define TRGT_VAS_A24                0x00010000
#define TRGT_VAS_A16                0x00000000
#define TRGT_VAS_CRCSR              0x00050000
#define TRGT_PGM_PROGRAM            0x00004000
#define TRGT_PGM_DATA               0x00000000
#define TRGT_SUPER_P                0x00001000
#define TRGT_SUPER_NP               0x00000000
#define TRGT_VCT_BLT_EN             0x00000100
#define TRGT_VCT_NO_BLT             0x00000000
#define TRGT_LAS_IO                 0x00000001
#define TRGT_LAS_MEM                0x00000000

  /* 
   *  Special PCI target image register defines (SLSI) 
   */
#define SLSI_TRGT_PWEN              0x40000000
#define SLSI0_TRGT_VDW_16           0x00000000
#define SLSI0_TRGT_VDW_32           0x00100000
#define SLSI1_TRGT_VDW_16           0x00000000
#define SLSI1_TRGT_VDW_32           0x00200000
#define SLSI2_TRGT_VDW_16           0x00000000
#define SLSI2_TRGT_VDW_32           0x00400000
#define SLSI3_TRGT_VDW_16           0x00000000
#define SLSI3_TRGT_VDW_32           0x00800000
#define SLSI0_TRGT_PGM_PRGM         0x00001000
#define SLSI0_TRGT_PGM_DATA         0x00000000
#define SLSI1_TRGT_PGM_PRGM         0x00002000
#define SLSI1_TRGT_PGM_DATA         0x00000000
#define SLSI2_TRGT_PGM_PRGM         0x00004000
#define SLSI2_TRGT_PGM_DATA         0x00000000
#define SLSI3_TRGT_PGM_PRGM         0x00008000
#define SLSI3_TRGT_PGM_DATA         0x00000000
#define SLSI0_TRGT_SUPER_P          0x00000100
#define SLSI0_TRGT_SUPER_NP         0x00000000
#define SLSI1_TRGT_SUPER_P          0x00000200
#define SLSI1_TRGT_SUPER_NP         0x00000000
#define SLSI2_TRGT_SUPER_P          0x00000400
#define SLSI2_TRGT_SUPER_NP         0x00000000
#define SLSI3_TRGT_SUPER_P          0x00000800
#define SLSI3_TRGT_SUPER_NP         0x00000000
#define SLSI_TRGT_LAS_IO            0x00000001
#define SLSI_TRGT_LAS_MEM           0x00000000

  /* 
   *  Interrupt register defines (LINT_EN/LINT_STAT/VINT_EN/VINT_STAT) 
   */
#define LINT_DIS_ALL                0xFF000800  /* and'd */
#define LINT_CLR_ALL                ~LINT_DIS_ALL       /* or'd */
#define VINT_DIS_ALL                0x01F0E800  /* and'd */
#define VINT_CLR_ALL                ~VINT_DIS_ALL       /* or'd */

  /* 
   *  Master control register defines (MAST_CTL) 
   */
#define MAXRTRY(x)                  (((x) & 0x3C0 ) << 22)
#define PWON_CNT_128                0x00000000
#define PWON_CNT_256                0x01000000
#define PWON_CNT_512                0x02000000
#define PWON_CNT_1024               0x03000000
#define PWON_CNT_2048               0x04000000
#define PWON_CNT_4096               0x05000000
#define PWON_EARLY_RELEASE          0x0f000000
#define VRL_0                       0x00000000
#define VRL_1                       0x00400000
#define VRL_2                       0x00800000
#define VRL_3                       0x00C00000
#define VRM_DEMAND                  0x00000000
#define VRM_FAIR                    0x00200000
#define	VREL_ON_REQ                 0x00100000
#define VREL_WHEN_DONE              0x00000000
#define VOWN_ACQ_AND_HOLD_BUS       0x00080000
#define VOWN_RELEASE_BUS            0x00000000
#define VOWN_ACK_NOT_OWNED          0x00000000
#define VOWN_ACK_OWNED_AND_HELD     0x00040000
#define PABS_32                     0x00000000
#define PABS_64                     0x00001000
#define BUS_NO(x)                   ((x) & 0xFF)

  /* 
   *  Miscellaneous control register defines (MISC_CTL) 
   */
#define VBTO_DISABLE                0x00000000
#define VBTO_16US                   0x10000000
#define VBTO_32US                   0x20000000
#define VBTO_64US                   0x30000000
#define VBTO_128US                  0x40000000
#define VBTO_256US                  0x50000000
#define VBTO_512US                  0x60000000
#define VBTO_1024US                 0x70000000
#define VARB_RNDRBN                 0x00000000
#define VARB_PRIORITY               0x04000000
#define VARB_TOUT_DISABL            0x00000000
#define VARB_TOUT_16US              0x01000000
#define	VARB_TOUT_256US             0x02000000
#define SW_LRST                     0x00800000
#define SW_SYSRST                   0x00400000
#define BI_MODE_EN                  0x00100000
#define BI_MODE_DIS                 0xFFEFFFFF
#define ENGBI_MODE                  0x00080000
#define RESCIND_DTACK_EN            0x00040000
#define SYSCON                      0x00020000
#define V64AUTO_ID                  0x0000FF00

  /* 
   *  VME slave image registers
   */
#define SLAVE_PWEN                  0x40000000
#define SLAVE_PREN                  0x20000000
#define SLAVE_PGM_PROGRAM           0x00800000
#define SLAVE_PGM_DATA              0x00400000
#define SLAVE_SUPER_NP              0x00200000
#define SLAVE_SUPER_P               0x00100000
#define SLAVE_VAS_A32               0x00020000
#define SLAVE_VAS_A24               0x00010000
#define SLAVE_VAS_A16               0x00000000
#define SLAVE_VAS_USER2             0x00070000
#define SLAVE_VAS_USER1             0x00060000
#define SLAVE_LD64EN                0x00000080
#define SLAVE_LLRMW                 0x00000040
#define SLAVE_LAS_CONFIG            0x00000002
#define SLAVE_LAS_IO                0x00000001
#define SLAVE_LAS_MEM               0x00000000

  /*
   * VMEbus AM Code Error Log (VAMERR)
   */
#define V_STAT                      0x00800000

  /* 
   *  DMA Transfer Control Register (DCTL)
   */
#define DMA_RD                      0x00000000
#define DMA_WR                      0x80000000
#define DMA_BLT                     0x00000100
#define DMA_LD64EN                  0x00000080

  /* 
   * DMA General Control/Status Register (DGCS)
   */
#define DMA_GO                      0x80000000
#define DMA_STOP_REQ                0x40000000
#define DMA_HALT_REQ                0x20000000
#define DMA_CHAIN                   0x08000000
#define DMA_VON_UNTIL_DONE          0x00000000