universe.h

universeII驱动

  /*
   * Interrupt status/id out register
   */
#define UNIV_STATID__STAT_ID(x)             ((unsigned int)(((x) & 0xFF) << 24))

  /*
   * VIRQ status/id register
   */
#define UNIV_V_STATID__ERR                  0x00000100
#define UNIV_V_STATID__STATID               0x000000FF


  /*
   * Semaphore registers
   */
#define UNIV_SEM_MIN                        0
#define UNIV_SEM_MAX                        7
#define UNIV_SEM__SEM                       0x80
#define UNIV_SEM__TAG                       0x7F


  /* 
   *  Master control register
   */
#define UNIV_MAST_CTL__MAXRTRY              0xF0000000
#define UNIV_MAST_CTL__MAXRTRY__960         0xF0000000
#define UNIV_MAST_CTL__MAXRTRY__896         0xE0000000
#define UNIV_MAST_CTL__MAXRTRY__832         0xD0000000
#define UNIV_MAST_CTL__MAXRTRY__768         0xC0000000
#define UNIV_MAST_CTL__MAXRTRY__704         0xB0000000
#define UNIV_MAST_CTL__MAXRTRY__640         0xA0000000
#define UNIV_MAST_CTL__MAXRTRY__576         0x90000000
#define UNIV_MAST_CTL__MAXRTRY__512         0x80000000
#define UNIV_MAST_CTL__MAXRTRY__448         0x70000000
#define UNIV_MAST_CTL__MAXRTRY__384         0x60000000
#define UNIV_MAST_CTL__MAXRTRY__320         0x50000000
#define UNIV_MAST_CTL__MAXRTRY__256         0x40000000
#define UNIV_MAST_CTL__MAXRTRY__192         0x30000000
#define UNIV_MAST_CTL__MAXRTRY__128         0x20000000
#define UNIV_MAST_CTL__MAXRTRY__64          0x10000000
#define UNIV_MAST_CTL__MAXRTRY__FOREVER     0x00000000
#define UNIV_MAST_CTL__PWON                 0x0F000000
#define UNIV_MAST_CTL__PWON__EARLY_RELEASE  0x0F000000
#define UNIV_MAST_CTL__PWON__4096           0x05000000
#define UNIV_MAST_CTL__PWON__2048           0x04000000
#define UNIV_MAST_CTL__PWON__1024           0x03000000
#define UNIV_MAST_CTL__PWON__512            0x02000000
#define UNIV_MAST_CTL__PWON__256            0x01000000
#define UNIV_MAST_CTL__PWON__128            0x00000000
#define UNIV_MAST_CTL__VRL                  0x00C00000
#define UNIV_MAST_CTL__VRL__3               0x00C00000
#define UNIV_MAST_CTL__VRL__2               0x00800000
#define UNIV_MAST_CTL__VRL__1               0x00400000
#define UNIV_MAST_CTL__VRL__0               0x00000000
#define UNIV_MAST_CTL__VRM                  0x00200000
#define UNIV_MAST_CTL__VRM__FAIR            0x00200000
#define UNIV_MAST_CTL__VRM__DEMAND          0x00000000
#define	UNIV_MAST_CTL__VREL                 0x00100000
#define	UNIV_MAST_CTL__VREL__ON_REQ         0x00100000
#define UNIV_MAST_CTL__VREL__WHEN_DONE      0x00000000
#define UNIV_MAST_CTL__VOWN                 0x00080000
#define UNIV_MAST_CTL__VOWN_ACK             0x00040000
#define UNIV_MAST_CTL__PABS                 0x00001000
#define UNIV_MAST_CTL__PABS__128            0x00002000
#define UNIV_MAST_CTL__PABS__64             0x00001000
#define UNIV_MAST_CTL__PABS__32             0x00000000
#define UNIV_MAST_CTL__BUS_NO(x)            ((x) & 0xFF)


  /* 
   *  Miscellaneous control register
   */
#define UNIV_MISC_CTL__VBTO                 0xF0000000
#define UNIV_MISC_CTL__VBTO__1024           0x70000000
#define UNIV_MISC_CTL__VBTO__512            0x60000000
#define UNIV_MISC_CTL__VBTO__256            0x50000000
#define UNIV_MISC_CTL__VBTO__128            0x40000000
#define UNIV_MISC_CTL__VBTO__64             0x30000000
#define UNIV_MISC_CTL__VBTO__32             0x20000000
#define UNIV_MISC_CTL__VBTO__16             0x10000000
#define UNIV_MISC_CTL__VBTO__DISABLE        0x00000000
#define UNIV_MISC_CTL__VARB                 0x04000000
#define UNIV_MISC_CTL__VARB__PRIORITY       0x04000000
#define UNIV_MISC_CTL__VARB__ROUND_ROBIN    0x00000000
#define	UNIV_MISC_CTL__VARBTO               0x03000000
#define	UNIV_MISC_CTL__VARBTO__256          0x02000000
#define UNIV_MISC_CTL__VARBTO__16           0x01000000
#define UNIV_MISC_CTL__VARBTO__DISABLE      0x00000000
#define UNIV_MISC_CTL__SW_LRST              0x00800000
#define UNIV_MISC_CTL__SW_SRST              0x00400000
#define UNIV_MISC_CTL__BI                   0x00100000
#define UNIV_MISC_CTL__ENGBI                0x00080000
#define UNIV_MISC_CTL__RESCIND              0x00040000
#define UNIV_MISC_CTL__SYSCON               0x00020000
#define UNIV_MISC_CTL__V64AUTO              0x00010000


 /*
  * Miscellaneous status register
  */
#define UNIV_MISC_STAT__LCLSIZE__64         0x40000000
#define UNIV_MISC_STAT__DY4AUTO             0x08000000
#define UNIV_MISC_STAT__MYBBSY              0x00200000
#define UNIV_MISC_STAT__DY4_DONE            0x00080000
#define UNIV_MISC_STAT__TXFE                0x00040000
#define UNIV_MISC_STAT__RXFE                0x00020000
#define UNIV_MISC_STAT__DY4AUTOID           0x0000FF00

  /*
   * User address modifier codes register
   */
#define UNIV_USER_AM__USER1AM               0x3C000000
#define UNIV_USER_AM__USER2AM               0x003C0000

  /*
   * Universe II specific register (used to control filters).
   */
#define UNIV_U2SPEC__DS                     0x00004000
#define UNIV_U2SPEC__AS                     0x00002000
#define UNIV_U2SPEC__DTKFLT                 0x00001000
#define UNIV_U2SPEC__MAST                   0x00000400
#define UNIV_U2SPEC__READ                   0x00000300
#define UNIV_U2SPEC__READ__DEFAULT          0x00000000
#define UNIV_U2SPEC__READ__FAST             0x00000100
#define UNIV_U2SPEC__READ__NODELAY          0x00000200
#define UNIV_U2SPEC__POS                    0x00000004
#define UNIV_U2SPEC__PRE                    0x00000001

  /* 
   * VMEbus slave image control registers
   */
#define UNIV_VSI_CTL__EN                    0x80000000
#define UNIV_VSI_CTL__PWEN                  0x40000000
#define UNIV_VSI_CTL__PREN                  0x20000000
#define UNIV_VSI_CTL__PGM                   0x00C00000
#define UNIV_VSI_CTL__PGM__BOTH             0x00C00000
#define UNIV_VSI_CTL__PGM__PROGRAM          0x00800000
#define UNIV_VSI_CTL__PGM__DATA             0x00400000
#define UNIV_VSI_CTL__SUPER                 0x00300000
#define UNIV_VSI_CTL__SUPER__BOTH           0x00300000
#define UNIV_VSI_CTL__SUPER__SUPER          0x00200000
#define UNIV_VSI_CTL__SUPER__USER           0x00100000
#define UNIV_VSI_CTL__VAS                   0x00070000
#define UNIV_VSI_CTL__VAS__USER2            0x00070000
#define UNIV_VSI_CTL__VAS__USER1            0x00060000
#define UNIV_VSI_CTL__VAS__A32              0x00020000
#define UNIV_VSI_CTL__VAS__A24              0x00010000
#define UNIV_VSI_CTL__VAS__A16              0x00000000
#define UNIV_VSI_CTL__LD64EN                0x00000080
#define UNIV_VSI_CTL__LLRMW                 0x00000040 /* Don't USE !! */
#define UNIV_VSI_CTL__LAS                   0x00000003
#define UNIV_VSI_CTL__LAS__CONFIG           0x00000002
#define UNIV_VSI_CTL__LAS__IO               0x00000001
#define UNIV_VSI_CTL__LAS__MEM              0x00000000

#define UNIV_VSI__4KB_MASK                  0x00000FFF /* LSI 0,4 */
#define UNIV_VSI__64KB_MASK                 0x0000FFFF /* LSI 1,2,3,5,6,7 */


  /* 
   *  Location monitor control register
   */
#define UNIV_LM_CTL__EN                     0x80000000
#define UNIV_LM_CTL__PGM                    0x00C00000
#define UNIV_LM_CTL__PGM__BOTH              0x00C00000
#define UNIV_LM_CTL__PGM__PROGRAM           0x00800000
#define UNIV_LM_CTL__PGM__DATA              0x00400000
#define UNIV_LM_CTL__SUPER                  0x00300000
#define UNIV_LM_CTL__SUPER__BOTH            0x00300000
#define UNIV_LM_CTL__SUPER__SUPER           0x00200000
#define UNIV_LM_CTL__SUPER__USER            0x00100000
#define UNIV_LM_CTL__VAS                    0x00030000
#define UNIV_LM_CTL__VAS__USER2             0x00070000
#define UNIV_LM_CTL__VAS__USER1             0x00060000
#define UNIV_LM_CTL__VAS__A32               0x00020000
#define UNIV_LM_CTL__VAS__A24               0x00010000
#define UNIV_LM_CTL__VAS__A16               0x00000000


  /* 
   * VMEbus register access control register
   */
#define UNIV_VRAI_CTL__EN                   0x80000000
#define UNIV_VRAI_CTL__PGM                  0x00C00000
#define UNIV_VRAI_CTL__PGM__BOTH            0x00C00000
#define UNIV_VRAI_CTL__PGM__PROGRAM         0x00800000
#define UNIV_VRAI_CTL__PGM__DATA            0x00400000
#define UNIV_VRAI_CTL__SUPER                0x00300000
#define UNIV_VRAI_CTL__SUPER__BOTH          0x00300000
#define UNIV_VRAI_CTL__SUPER__SUPER         0x00200000
#define UNIV_VRAI_CTL__SUPER__USER          0x00100000
#define UNIV_VRAI_CTL__VAS                  0x00070000
#define UNIV_VRAI_CTL__VAS__USER2           0x00070000
#define UNIV_VRAI_CTL__VAS__USER1           0x00060000
#define UNIV_VRAI_CTL__VAS__A32             0x00020000
#define UNIV_VRAI_CTL__VAS__A24             0x00010000
#define UNIV_VRAI_CTL__VAS__A16             0x00000000


 /*
  * VMEbus CSR control register
  */
#define UNIV_VCSR_CTL__EN                   0x80000000
#define UNIV_VCSR_CTL__LAS                  0x00000003
#define UNIV_VCSR_CTL__LAS__CONFIG          0x00000002
#define UNIV_VCSR_CTL__LAS__IO              0x00000001
#define UNIV_VCSR_CTL__LAS__MEM             0x00000000

  /*
   * VMEbus CSR translation offset register
   */
#define UNIV_VCSR_TO__TO                    0xFFF80000

  /*
   * VMEbus AM code error log
   */
#define UNIV_V_AMERR__AMERR                 0xFC000000
#define UNIV_V_AMERR__IACK                  0x02000000
#define UNIV_V_AMERR__M_ERR                 0x01000000
#define UNIV_V_AMERR__V_STAT                0x00800000
#define UNIV_BERR_AM(status)  (((status) & UNIV_V_AMERR__AMERR) >> 26)

 /*
  * VMEbus CSR bit clear and set registers
  */
#define UNIV_VCSR__RESET                    0x80000000
#define UNIV_VCSR__SYSFAIL                  0x40000000
#define UNIV_VCSR__FAIL                     0x20000000

  /*
   * VMEbus CSR base address register
   */
#define UNIV_VCSR_BS__BS                    0xF8000000

#ifdef __cplusplus
}

#endif                          /* __cplusplus */

#endif                          /* __UNIVERSE_H */