universe.h

universeII驱动

#define UNIV_L_CMDERR__M_ERR                0x08000000
#define UNIV_L_CMDERR__L_STAT               0x00800000


  /* 
   *  DMA Transfer Control Register
   */
#define UNIV_DCTL__L2V                      0x80000000
#define UNIV_DCTL__VDW                      0x00C00000
#define UNIV_DCTL__VDW__D64                 0x00C00000
#define UNIV_DCTL__VDW__D32                 0x00800000
#define UNIV_DCTL__VDW__D16                 0x00400000
#define UNIV_DCTL__VDW__D8                  0x00000000
#define UNIV_DCTL__VAS                      0x00070000
#define UNIV_DCTL__VAS__USER2               0x00070000
#define UNIV_DCTL__VAS__USER1               0x00060000
#define UNIV_DCTL__VAS__A32                 0x00020000
#define UNIV_DCTL__VAS__A24                 0x00010000
#define UNIV_DCTL__VAS__A16                 0x00000000
#define UNIV_DCTL__PGM                      0x00004000
#define UNIV_DCTL__SUPER                    0x00001000
#define UNIV_DCTL__VCT                      0x00000100
#define UNIV_DCTL__LD64EN                   0x00000080


  /* 
   * DMA General Control/Status Register
   */
#define UNIV_DGCS__GO                       0x80000000
#define UNIV_DGCS__STOP_REQ                 0x40000000
#define UNIV_DGCS__HALT_REQ                 0x20000000
#define UNIV_DGCS__CHAIN                    0x08000000
#define UNIV_DGCS__VON                      0x00700000
#define UNIV_DGCS__VON__UNTIL_DONE          0x00000000
#define UNIV_DGCS__VON__256                 0x00100000
#define UNIV_DGCS__VON__512                 0x00200000
#define UNIV_DGCS__VON__1024                0x00300000
#define UNIV_DGCS__VON__2048                0x00400000
#define UNIV_DGCS__VON__4096                0x00500000
#define UNIV_DGCS__VON__8192                0x00600000
#define UNIV_DGCS__VON__16384               0x00700000
#define UNIV_DGCS__VOFF                     0x000f0000
#define UNIV_DGCS__VOFF__0                  0x00000000
#define UNIV_DGCS__VOFF__16                 0x00010000
#define UNIV_DGCS__VOFF__32                 0x00020000
#define UNIV_DGCS__VOFF__64                 0x00030000
#define UNIV_DGCS__VOFF__128                0x00040000
#define UNIV_DGCS__VOFF__256                0x00050000
#define UNIV_DGCS__VOFF__512                0x00060000
#define UNIV_DGCS__VOFF__1024               0x00070000
#define UNIV_DGCS__VOFF__2000               0x00080000
#define UNIV_DGCS__VOFF__4000               0x00090000
#define UNIV_DGCS__VOFF__8000               0x000a0000
#define UNIV_DGCS__ACT                      0x00008000
#define UNIV_DGCS__STOP                     0x00004000
#define UNIV_DGCS__HALT                     0x00002000
#define UNIV_DGCS__DONE                     0x00000800
#define UNIV_DGCS__LERR                     0x00000400
#define UNIV_DGCS__VERR                     0x00000200
#define UNIV_DGCS__P_ERR                    0x00000100
#define UNIV_DGCS__INT_STOP                 0x00000040
#define UNIV_DGCS__INT_HALT                 0x00000020
#define UNIV_DGCS__INT_DONE                 0x00000008
#define UNIV_DGCS__INT_LERR                 0x00000004
#define UNIV_DGCS__INT_VERR                 0x00000002
#define UNIV_DGCS__INT_P_ERR                0x00000001


  /*
   * DMA linked list update enabled register
   */
#define UNIV_D_LLUE__UPDATE                 0x80000000


  /*
   * PCI interrupt enable and status registers
   */
#define UNIV_LINT__LM3                      0x00800000
#define UNIV_LINT__LM2                      0x00400000
#define UNIV_LINT__LM1                      0x00200000
#define UNIV_LINT__LM0                      0x00100000
#define UNIV_LINT__LM(x)                    (0x00100000 << (x))
#define UNIV_LINT__MBOX3                    0x00080000
#define UNIV_LINT__MBOX2                    0x00040000
#define UNIV_LINT__MBOX1                    0x00020000
#define UNIV_LINT__MBOX0                    0x00010000
#define UNIV_LINT__MBOX(x)                  (0x00010000 << (x))
#define UNIV_LINT__ACFAIL                   0x00008000
#define UNIV_LINT__SYSFAIL                  0x00004000
#define UNIV_LINT__SW_INT                   0x00002000
#define UNIV_LINT__SW_IACK                  0x00001000
#define UNIV_LINT__VERR                     0x00000400
#define UNIV_LINT__LERR                     0x00000200
#define UNIV_LINT__DMA                      0x00000100
#define UNIV_LINT__VIRQ7                    0x00000080
#define UNIV_LINT__VIRQ6                    0x00000040
#define UNIV_LINT__VIRQ5                    0x00000020
#define UNIV_LINT__VIRQ4                    0x00000010
#define UNIV_LINT__VIRQ3                    0x00000008
#define UNIV_LINT__VIRQ2                    0x00000004
#define UNIV_LINT__VIRQ1                    0x00000002
#define UNIV_LINT__VIRQ(x)                  (1 << (x))
#define UNIV_LINT__VOWN                     0x00000001
#define UNIV_MAX_IRQ                        23

#define UNIV_LINT_STAT_INT_PENDING      (UNIV_LINT__VOWN | \
                                         UNIV_LINT__VIRQ(1) | \
                                         UNIV_LINT__VIRQ(2) | \
                                         UNIV_LINT__VIRQ(3) | \
                                         UNIV_LINT__VIRQ(4) | \
                                         UNIV_LINT__VIRQ(5) | \
                                         UNIV_LINT__VIRQ(6) | \
                                         UNIV_LINT__VIRQ(7) | \
                                         UNIV_LINT__DMA | \
                                         UNIV_LINT__LERR | \
                                         UNIV_LINT__VERR | \
                                         UNIV_LINT__SW_IACK | \
                                         UNIV_LINT__SW_INT | \
                                         UNIV_LINT__SYSFAIL | \
                                         UNIV_LINT__ACFAIL | \
                                         UNIV_LINT__MBOX(0) | \
                                         UNIV_LINT__MBOX(1) | \
                                         UNIV_LINT__MBOX(2) | \
                                         UNIV_LINT__MBOX(3) | \
                                         UNIV_LINT__LM(0) | \
                                         UNIV_LINT__LM(1) | \
                                         UNIV_LINT__LM(2) | \
                                         UNIV_LINT__LM(3))

  /* Sometimes it's helpful to have all of the interrupt level/vectors in a
     single array.  These macros are useful for that purpose. In this case the
     first MAX_INT_LEVELS * MAX_INT_VECTORS elements are the vectored VME
     IRQ's.  The other interrupt levels sit on top of the VME IRQ's and are
     indexed by UNIV_VECTOR_IRQS + level.
   */
#define UNIV_VIRQS        7      /* Number of vectored VME irq's */
#define UNIV_VECTORS      256    /* Number of VIRQ vectors. */
#define UNIV_VECTOR_IRQS (UNIV_VIRQS * UNIV_VECTORS)
#define UNIV_IRQS         UNIV_VECTOR_IRQS + UNIV_MAX_IRQ + 1 

#define UNIV_INTERRUPT_INDEX(_lvl, _vec) \
(((1 <= (_lvl)) && (UNIV_VIRQS >= (_lvl))) ? \
(((_lvl) - 1) * UNIV_VECTORS) + (_vec) : UNIV_VECTOR_IRQS + (_lvl))

#define UNIV_INTERRUPT_LEVEL(_idx) \
((UNIV_VECTOR_IRQS > (_idx)) ? ((_idx) / UNIV_VECTORS + 1) : \
(_idx) - UNIV_VECTOR_IRQS)

#define UNIV_INTERRUPT_VECTOR(_idx) \
((UNIV_VECTOR_IRQS > (_idx)) ? (_idx) % UNIV_VECTORS : 0)


  /*
   * PCI interrupt map registers
   */
#define UNIV_LINT_MAP0__VIRQ7               0x70000000
#define UNIV_LINT_MAP0__VIRQ6               0x07000000
#define UNIV_LINT_MAP0__VIRQ5               0x00700000
#define UNIV_LINT_MAP0__VIRQ4               0x00070000
#define UNIV_LINT_MAP0__VIRQ3               0x00007000
#define UNIV_LINT_MAP0__VIRQ2               0x00000700
#define UNIV_LINT_MAP0__VIRQ1               0x00000070
#define UNIV_LINT_MAP0__VIRQ(virq,lint)     (((lint) & 0x07) << (4 * (virq)))
#define UNIV_LINT_MAP0__VOWN                0x00000007
#define UNIV_LINT_MAP0__VOWN_LEVEL(x)       (((x) & 0x07) << 0)
#define UNIV_LINT_MAP0__ACFAIL              0x70000000
#define UNIV_LINT_MAP1__ACFAIL_LEVEL(x)     (((x) & 0x07) << 28)
#define UNIV_LINT_MAP1__SYSFAIL             0x07000000
#define UNIV_LINT_MAP1__SYSFAIL_LEVEL(x)    (((x) & 0x07) << 24)
#define UNIV_LINT_MAP1__SWINT               0x00700000
#define UNIV_LINT_MAP1__SWINT_LEVEL(x)      (((x) & 0x07) << 20)
#define UNIV_LINT_MAP1__SWIACK              0x00070000
#define UNIV_LINT_MAP1__SWIACK_LEVEL(x)     (((x) & 0x07) << 16)
#define UNIV_LINT_MAP1__VERR                0x00000700
#define UNIV_LINT_MAP1__VERR_LEVEL(x)       (((x) & 0x07) << 8)
#define UNIV_LINT_MAP1__LERR                0x00000070
#define UNIV_LINT_MAP1__LERR_LEVEL(x)       (((x) & 0x07) << 4)
#define UNIV_LINT_MAP1__DMA                 0x00000007
#define UNIV_LINT_MAP1__DMA_LEVEL(x)        (((x) & 0x07) << 0)
#define UNIV_LINT_MAP2__LM3                 0x70000000
#define UNIV_LINT_MAP2__LM2                 0x07000000
#define UNIV_LINT_MAP2__LM1                 0x00700000
#define UNIV_LINT_MAP2__LM0                 0x00070000
#define UNIV_LINT_MAP2__LM(lm,lint)         (((lint) & 0x7) << ((4 * (lm)) + 16))
#define UNIV_LINT_MAP2__LM3                 0x70000000
#define UNIV_LINT_MAP2__MBOX3               0x00007000
#define UNIV_LINT_MAP2__MBOX2               0x00000700
#define UNIV_LINT_MAP2__MBOX1               0x00000070
#define UNIV_LINT_MAP2__MBOX0               0x00000007
#define UNIV_LINT_MAP2__MBOX(mb,lint)       (((lint) & 0x7) << (4 * (mb)))


  /*
   * VMEbus interrupt enable and status registers
   */
#define UNIV_VINT__SW_INT7                  0x80000000
#define UNIV_VINT__SW_INT6                  0x40000000
#define UNIV_VINT__SW_INT5                  0x20000000
#define UNIV_VINT__SW_INT4                  0x10000000
#define UNIV_VINT__SW_INT3                  0x08000000
#define UNIV_VINT__SW_INT2                  0x04000000
#define UNIV_VINT__SW_INT1                  0x02000000
#define UNIV_VINT__MBOX3                    0x00080000
#define UNIV_VINT__MBOX2                    0x00040000
#define UNIV_VINT__MBOX1                    0x00020000
#define UNIV_VINT__MBOX0                    0x00010000
#define UNIV_VINT__SW_INT                   0x00001000
#define UNIV_VINT__VERR                     0x00000400
#define UNIV_VINT__LERR                     0x00000200
#define UNIV_VINT__DMA                      0x00000100
#define UNIV_VINT__LINT7                    0x00000080
#define UNIV_VINT__LINT6                    0x00000040
#define UNIV_VINT__LINT5                    0x00000020
#define UNIV_VINT__LINT4                    0x00000010
#define UNIV_VINT__LINT3                    0x00000008
#define UNIV_VINT__LINT2                    0x00000004
#define UNIV_VINT__LINT1                    0x00000002
#define UNIV_VINT__LINT0                    0x00000001


  /*
   * VMEbus interrupt map registers
   */
#define UNIV_VINT_MAP0__LINT7               0x70000000
#define UNIV_VINT_MAP0__LINT6               0x07000000
#define UNIV_VINT_MAP0__LINT5               0x00700000
#define UNIV_VINT_MAP0__LINT4               0x00070000
#define UNIV_VINT_MAP0__LINT3               0x00007000
#define UNIV_VINT_MAP0__LINT2               0x00000700
#define UNIV_VINT_MAP0__LINT1               0x00000070
#define UNIV_VINT_MAP0__LINT0               0x00000007
#define UNIV_VINT_MAP0__LINT(lint,vint)     (((vint) & 0x7) << (4 * (lint))
#define UNIV_VINT_MAP1__SW_INT              0x00070000
#define UNIV_VINT_MAP1__SW_INT_LEVEL(x)     (((x) & 0x7) << 16)
#define UNIV_VINT_MAP1__VERR                0x00000700
#define UNIV_VINT_MAP1__VERR_LEVEL(x)       (((x) & 0x7) << 8)
#define UNIV_VINT_MAP1__LERR                0x00000070
#define UNIV_VINT_MAP1__LERR_LEVEL(x)       (((x) & 0x7) << 4)
#define UNIV_VINT_MAP1__DMA                 0x00000007
#define UNIV_VINT_MAP1__DMA_LEVEL(x)        (((x) & 0x7) << 0)
#define UNIV_VINT_MAP2__MBOX3               0x00007000
#define UNIV_VINT_MAP2__MBOX2               0x00000700
#define UNIV_VINT_MAP2__MBOX1               0x00000070
#define UNIV_VINT_MAP2__MBOX0               0x00000007
#define UNIV_VINT_MAP2__MBOX(mb,vint)       (((mb) & 0x7) << (4 * (vint))