universe.h

universeII驱动

/*
===============================================================================
                            COPYRIGHT NOTICE

    Copyright (C) 2001-2003 VMIC
    International Copyright Secured.  All Rights Reserved.

-------------------------------------------------------------------------------

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

   o Redistributions of source code must retain the above copyright notice, this
     list of conditions and the following disclaimer.
   o Redistributions in binary form must reproduce the above copyright notice,
     this list of conditions and the following disclaimer in the documentation
     and/or other materials provided with the distribution.
   o Neither the name of VMIC nor the names of its contributors may be used to
     endorse or promote products derived from this software without specific
     prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

===============================================================================
*/


#ifndef __UNIVERSE_H
#define __UNIVERSE_H

#ifdef __cplusplus
extern "C"
{

#endif                          /* __cplusplus */


  /* 
   *  Universe device registers 
   */
#define UNIV_PCI_ID     0x000   /* PCI configuration space ID register */
#define UNIV_PCI_CSR    0x004   /* PCI configuration space control and status */
#define UNIV_PCI_CLASS  0x008   /* PCI configuration class register */
#define UNIV_PCI_MISC0  0x00C   /* PCI configuration miscellaneous 0 regster */
#define UNIV_PCI_BS0    0x010   /* PCI configuration base address 0 register */
#define UNIV_PCI_BS1    0x014   /* PCI configuration base address 1 register */
#define UNIV_PCI_MISC1  0x03C   /* PCI configuration miscellaneous 1 regster */
  /* PCI target image (x) control register */
#define UNIV_LSI_CTL(x) 0x100 + ((x) * 0x14) + (((x) >= 4) ? 0x50 : 0)
#define UNIV_LSI_BS(x)  UNIV_LSI_CTL(x) + 0x4   /* PCI target image (x) base
                                                   address register */
#define UNIV_LSI_BD(x)  UNIV_LSI_CTL(x) + 0x8   /* PCI target image (x) bound
                                                   address register */
#define UNIV_LSI_TO(x)  UNIV_LSI_CTL(x) + 0xC   /* PCI target image (x)
                                                   translation offset
                                                   register */
#define UNIV_SCYC_CTL   0x170   /* Special cycle control register */
#define UNIV_SCYC_ADDR  0x174   /* Special cycle PCI bus address register */
#define UNIV_SCYC_EN    0x178   /* Special cycle swap/compare enable register */
#define UNIV_SCYC_CMP   0x17C   /* Special cycle compare data register */
#define UNIV_SCYC_SWP   0x180   /* Special cycle swap data register */
#define UNIV_LMISC      0x184   /* PCI micellaneous register */
#define UNIV_SLSI       0x188   /* Special PCI target image register */
#define UNIV_DCTL       0x200   /* DMA transfer control register */
#define UNIV_DTBC       0x204   /* DMA transfer byte count register */
#define UNIV_DLA        0x208   /* DMA PCI bus address register */
#define UNIV_DVA        0x210   /* DMA VME address register */
#define UNIV_DCPP       0x218   /* DMA command packet pointer */
#define UNIV_DGCS       0x220   /* DMA general control and status register */
#define UNIV_D_LLUE     0x224   /* DMA linked list update enable register */
#define UNIV_LINT_EN    0x300   /* PCI interrupt enable register */
#define UNIV_LINT_STAT  0x304   /* PCI interrupt status register */
#define UNIV_LINT_MAP0  0x308   /* PCI interrupt map 0 register */
#define UNIV_LINT_MAP1  0x30c   /* PCI interrupt map 1 register */
#define UNIV_VINT_EN    0x310   /* VME interrupt enable register */
#define UNIV_VINT_STAT  0x314   /* VME interrupt status register */
#define UNIV_VINT_MAP0  0x318   /* VME interrupt map 0 register */
#define UNIV_VINT_MAP1  0x31c   /* VME interrupt map 1 register */
#define UNIV_STATID     0x320   /* Interrupt status/id out register */
#define UNIV_V_STATID(x)  (0x324 + (((x) - 1) * 4 ))    /* VIRQ(x) status/id in
                                                           register */
#define UNIV_LINT_MAP2  0x340   /* PCI interrupt map 2 register */
#define UNIV_VINT_MAP2  0x344   /* VME interrupt map 1 register */
#define UNIV_MBOX(x)    0x348 + ((x) * 4)       /* Mailbox (x) register */
#define UNIV_SEMA(x)    0x358 + (x)     /* Semaphore(x) register, byte access */
#define UNIV_MAST_CTL   0x400   /* Master control register */
#define UNIV_MISC_CTL   0x404   /* Miscellaneous control register */
#define UNIV_MISC_STAT  0x408   /* Miscellaneous status register */
#define UNIV_USER_AM    0x40C   /* User address modifier codes register */
#define UNIV_U2SPEC     0x4FC   /* Universe II Specific Register */
  /* Slave image (x) control register */
#define UNIV_VSI_CTL(x) 0xF00 + ((x) * 0x14) + (((x) >= 4) ? 0x40 : 0)
#define UNIV_VSI_BS(x)  UNIV_VSI_CTL(x) + 0x4   /* Slave image (x) base address
                                                   register */
#define UNIV_VSI_BD(x)  UNIV_VSI_CTL(x) + 0x8   /* Slave image (x) bound address
                                                   register */
#define UNIV_VSI_TO(x)  UNIV_VSI_CTL(x) + 0xC   /* Slave image (x) translation
                                                   offset register */
#define UNIV_LM_CTL     0xF64   /* Location monitor control register */
#define UNIV_LM_BS      0xF68   /* Location monitor base address register */
#define UNIV_VRAI_CTL   0xF70   /* VME register access image control register */
#define UNIV_VRAI_BS    0xF74   /* VME register access image base address
                                   register */
#define UNIV_VCSR_CTL   0xF80   /* VMEbus CSR control register */
#define UNIV_VCSR_TO    0xF84   /* VMEbus CSR translation offset register */
#define UNIV_V_AMERR    0xF88   /* VMEbus AM code error log */
#define UNIV_VAERR      0xF8C   /* VMEbus address error log */
#define UNIV_VCSR_CLR   0xFF4   /* VMEbus CSR bit clear register */
#define UNIV_VCSR_SET   0xFF8   /* VMEbus CSR bit set register */
#define UNIV_VCSR_BS    0xFFC   /* VMEbus CSR base address register */

  /* 
   *  PCI Configuration space control and status register 
   */
#define UNIV_PCI_CSR__D_PE                  0x80000000
#define UNIV_PCI_CSR__S_SERR                0x40000000
#define UNIV_PCI_CSR__R_MA                  0x20000000
#define UNIV_PCI_CSR__R_TA                  0x10000000
#define UNIV_PCI_CSR__S_TA                  0x08000000
#define UNIV_PCI_CSR__DEVSEL                0x06000000
#define UNIV_PCI_CSR__DP_D                  0x01000000
#define UNIV_PCI_CSR__TFBBC                 0x00800000
#define UNIV_PCI_CSR__MFBBC                 0x00000200
#define UNIV_PCI_CSR__SERR_EN               0x00000100
#define UNIV_PCI_CSR__WAIT                  0x00000080
#define UNIV_PCI_CSR__PERESP                0x00000040
#define UNIV_PCI_CSR__VGAPS                 0x00000020
#define UNIV_PCI_CSR__MWI_EN                0x00000010
#define UNIV_PCI_CSR__SC                    0x00000008
#define UNIV_PCI_CSR__BM                    0x00000004
#define UNIV_PCI_CSR__MS                    0x00000002
#define UNIV_PCI_CSR__IOS                   0x00000001


  /*
   * PCI configuration class registers
   */
#define UNIV_PCI_CLASS__BASE                0xFF000000
#define UNIV_PCI_CLASS__SUB                 0x00FF0000
#define UNIV_PCI_CLASS__PROG                0x0000FF00
#define UNIV_PCI_CLASS__RID                 0x000000FF


  /*
   * PCI configuration miscellaneous 0 register
   */
#define UNIV_PCI_MISC0__BISTC               0x80000000
#define UNIV_PCI_MISC0__SBIST               0x40000000
#define UNIV_PCI_MISC0__CCODE               0x0F000000
#define UNIV_PCI_MISC0__MFUNCT              0x00800000
#define UNIV_PCI_MISC0__LAYOUT              0x003F0000
#define UNIV_PCI_MISC0__LTIMER              0x0000F800


  /*
   * PCI configuration miscellaneous 1 register
   */
#define UNIV_PCI_MISC1__MAX_LAT             0xFF000000
#define UNIV_PCI_MISC1__MIN_GNT             0x00FF0000
#define UNIV_PCI_MISC1__INT_PIN             0x0000FF00
#define UNIV_PCI_MISC1__INT_LINE            0x000000FF


  /* 
   *  PCI target image control registers
   */
#define UNIV_LSI_CTL__EN                    0x80000000
#define UNIV_LSI_CTL__PWEN                  0x40000000
#define UNIV_LSI_CTL__VDW                   0x00C00000
#define UNIV_LSI_CTL__VDW__D64              0x00C00000
#define UNIV_LSI_CTL__VDW__D32              0x00800000
#define UNIV_LSI_CTL__VDW__D16              0x00400000
#define UNIV_LSI_CTL__VDW__D8               0x00000000
#define UNIV_LSI_CTL__VAS                   0x00070000
#define UNIV_LSI_CTL__VAS__USER2            0x00070000
#define UNIV_LSI_CTL__VAS__USER1            0x00060000
#define UNIV_LSI_CTL__VAS__CRCSR            0x00050000
#define UNIV_LSI_CTL__VAS__A32              0x00020000
#define UNIV_LSI_CTL__VAS__A24              0x00010000
#define UNIV_LSI_CTL__VAS__A16              0x00000000
#define UNIV_LSI_CTL__PGM                   0x00004000
#define UNIV_LSI_CTL__SUPER                 0x00001000
#define UNIV_LSI_CTL__VCT                   0x00000100
#define UNIV_LSI_CTL__LAS                   0x00000001

#define UNIV_LSI__4KB_MASK                  0x00000FFF /* LSI 0,4 */
#define UNIV_LSI__64KB_MASK                 0x0000FFFF /* LSI 1,2,3,5,6,7 */

  /*
   * Special cycle control register
   */
#define UNIV_SCYC_CTL__LAS                  0x00000004
#define UNIV_SCYC_CTL__SCYC                 0x00000003
#define UNIV_SCYC_CTL__SCYC__RMW            0x00000001
#define UNIV_SCYC_CTL__SCYC__ADOH           0x00000002
#define UNIV_SCYC_CTL__SCYC__DISABLE        0x00000000

#define SCYC_EN__MASK                       0xFFFFFFFF
#define SCYC_CMP__TO_SET                    0x00000000 /* sysBusTas */
#define SCYC_SWP__TO_SET                    0xFFFFFFFF /* sysBusTas */

#define SCYC_CMP__TO_CLR                    0xFFFFFFFF /* sysBusTasClear */
#define SCYC_SWP__TO_CLR                    0x00000000 /* sysBusTasClear */

  /*
   * PCI miscellaneous register
   */
#define UNIV_LMISC__CRT                     0xF0000000
#define UNIV_LMISC__CWT                     0x07000000
#define UNIV_LMISC__CWT__512                0x06000000
#define UNIV_LMISC__CWT__256                0x05000000
#define UNIV_LMISC__CWT__128                0x04000000
#define UNIV_LMISC__CWT__32                 0x02000000
#define UNIV_LMISC__CWT__64                 0x03000000
#define UNIV_LMISC__CWT__16                 0x01000000


  /* 
   *  Special PCI target image register
   */
#define UNIV_SLSI__EN                       0x80000000
#define UNIV_SLSI__PWEN                     0x40000000
#define UNIV_SLSI__VDW(x)                   (0x00100000 << (x))
#define UNIV_SLSI__VDW__D32(x)              (0x00100000 << (x))
#define UNIV_SLSI__VDW__D16(x)              0x00000000
#define UNIV_SLSI__PGM(x)                   (0x00001000 << (x))
#define UNIV_SLSI__SUPER(x)                 (0x00000100 << (x))
#define UNIV_SLSI__BS                       0x000000FC
#define UNIV_SLSI__LAS                      0x00000001


  /*
   * PCI command error log register
   */
#define UNIV_L_CMDERR__CMDERR               0xF0000000