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📄 v_blast.mdl

📁 v-blast的仿真
💻 MDL
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	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Matrix\nConcatenate"
	  DstPort		  3
	}
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	  SrcPort		  1
	  DstBlock		  "Matrix\nConcatenate"
	  DstPort		  4
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	Line {
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	  SrcPort		  1
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	  DstPort		  1
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	  SrcPort		  1
	  DstBlock		  "AWGN\nChannel1"
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	}
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	  SrcPort		  1
	  DstBlock		  "AWGN\nChannel2"
	  DstPort		  1
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	  SrcPort		  1
	  DstBlock		  "AWGN\nChannel3"
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	}
	Line {
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	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
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	  SrcPort		  1
	  DstBlock		  "Out2"
	  DstPort		  1
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	Line {
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	  SrcPort		  1
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	  DstPort		  1
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	  DstPort		  1
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	Line {
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	    }
	    Branch {
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	      DstPort		      1
	    }
	  }
	  Branch {
	    Points		    [0, 35]
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      BlockType		      SubSystem
      Name		      "Subsystem1"
      Ports		      [1, 4]
      Position		      [355, 120, 400, 185]
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      System {
	Name			"Subsystem1"
	Location		[2, 82, 1270, 753]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [90, 418, 120, 432]
	  IconDisplay		  "Port number"
	}
	Block {

	  BlockType		  Reference
	  Name			  "AWGN\nChannel"
	  Ports			  [1, 1]
	  Position		  [640, 71, 735, 129]
	SourceBlock	"commchan2/AWGN\nChannel"
	  SourceType		  "AWGN Channel"
	  ShowPortLabels	  "FromPortIcon"
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	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "1100"
	  noiseMode		  "Signal to noise ratio  (SNR)"
	  EbNodB		  "SNR"
	  EsNodB		  "10"
	  SNRdB			  "SNR"
	  bitsPerSym		  "1"
	  Ps			  "0.1"
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	  variance		  "1"
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	Block {

	  BlockType		  Reference
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	  Position		  [645, 176, 740, 234]
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	  SourceType		  "AWGN Channel"
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	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "1200"
	  noiseMode		  "Signal to noise ratio  (SNR)"
	  EbNodB		  "SNR"
	  EsNodB		  "10"
	  SNRdB			  "SNR"
	  bitsPerSym		  "1"
	  Ps			  "0.1"
	  Tsym			  "14e-5"
	  variance		  "1"
	}
	Block {

	  BlockType		  Reference
	  Name			  "AWGN\nChannel2"
	  Ports			  [1, 1]
	  Position		  [650, 291, 745, 349]
	SourceBlock	"commchan2/AWGN\nChannel"
	  SourceType		  "AWGN Channel"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "1300"
	  noiseMode		  "Signal to noise ratio  (SNR)"
	  EbNodB		  "SNR"
	  EsNodB		  "10"
	  SNRdB			  "SNR"
	  bitsPerSym		  "1"
	  Ps			  "0.1"
	  Tsym			  "14e-5"
	  variance		  "1"
	}
	Block {

	  BlockType		  Reference
	  Name			  "AWGN\nChannel3"
	  Ports			  [1, 1]
	  Position		  [655, 416, 750, 474]
	SourceBlock	"commchan2/AWGN\nChannel"
	  SourceType		  "AWGN Channel"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "1400"
	  noiseMode		  "Signal to noise ratio  (SNR)"
	  EbNodB		  "SNR"
	  EsNodB		  "10"
	  SNRdB			  "SNR"
	  bitsPerSym		  "1"
	  Ps			  "0.1"
	  Tsym			  "14e-5"
	  variance		  "1"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant"
	  Position		  [95, 130, 125, 160]
	  Value			  "0"
	  SampleTime		  "160e-5"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant1"
	  Position		  [95, 200, 125, 230]
	  SampleTime		  "160e-5"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [95, 270, 125, 300]
	  Value			  "0"
	  SampleTime		  "160e-5"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant3"
	  Position		  [95, 340, 125, 370]
	  Value			  "0"
	  SampleTime		  "160e-5"
	}
	Block {

	  BlockType		  Reference
	  Name			  "Matrix\nConcatenate"
	  Ports			  [5, 1]
	  Position		  [260, 104, 345, 466]
	SourceBlock	"simulink/Math\nOperations/Matrix\nConcatenation"
	  SourceType		  "Matrix Concatenation"
	  numInports		  "5"
	  catMethod		  "Vertical"
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	Block {

	  BlockType		  Reference
	  Name			  "Multipath Rayleigh\nFading Channel"
	  Ports			  [1, 1]
	  Position		  [465, 71, 560, 129]
	SourceBlock	"commchan2/Multipath Rayleigh\nFading Channel"
	  SourceType		  "Multipath Rayleigh Fading Channel"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "1100"
	}
	Block {

	  BlockType		  Reference
	  Name			  "Multipath Rayleigh\nFading Channel1"
	  Ports			  [1, 1]
	  Position		  [465, 176, 560, 234]
	SourceBlock	"commchan2/Multipath Rayleigh\nFading Channel"
	  SourceType		  "Multipath Rayleigh Fading Channel"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "1200"
	}
	Block {

	  BlockType		  Reference
	  Name			  "Multipath Rayleigh\nFading Channel2"
	  Ports			  [1, 1]
	  Position		  [465, 291, 560, 349]
	SourceBlock	"commchan2/Multipath Rayleigh\nFading Channel"
	  SourceType		  "Multipath Rayleigh Fading Channel"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "1300"
	}
	Block {

	  BlockType		  Reference
	  Name			  "Multipath Rayleigh\nFading Channel3"
	  Ports			  [1, 1]
	  Position		  [465, 416, 560, 474]
	SourceBlock	"commchan2/Multipath Rayleigh\nFading Channel"
	  SourceType		  "Multipath Rayleigh Fading Channel"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData off
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "1400"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [880, 93, 910, 107]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
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	Block {
	  BlockType		  Outport
	  Name			  "Out2"
	  Position		  [880, 198, 910, 212]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out3"
	  Position		  [875, 313, 905, 327]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out4"
	  Position		  [880, 438, 910, 452]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Matrix\nConcatenate"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Matrix\nConcatenate"
	  DstPort		  1
	}
	Line {
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	  SrcPort		  1
	  DstBlock		  "Matrix\nConcatenate"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Matrix\nConcatenate"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Constant3"
	  SrcPort		  1
	  DstBlock		  "Matrix\nConcatenate"
	  DstPort		  4
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	Line {
	  SrcBlock		  "Multipath Rayleigh\nFading Channel"
	  SrcPort		  1
	  DstBlock		  "AWGN\nChannel"
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	}
	Line {
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	  SrcPort		  1
	  DstBlock		  "AWGN\nChannel1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Multipath Rayleigh\nFading Channel2"
	  SrcPort		  1
	  DstBlock		  "AWGN\nChannel2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Multipath Rayleigh\nFading Channel3"
	  SrcPort		  1
	  DstBlock		  "AWGN\nChannel3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AWGN\nChannel"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AWGN\nChannel1"
	  SrcPort		  1
	  DstBlock		  "Out2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AWGN\nChannel2"
	  SrcPort		  1
	  DstBlock		  "Out3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AWGN\nChannel3"
	  SrcPort		  1
	  DstBlock		  "Out4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Matrix\nConcatenate"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    Points		    [0, -80]
	    Branch {
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	      DstBlock		      "Multipath Rayleigh\nFading Channel"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Multipath Rayleigh\nFading Channel1"
	      DstPort		      1
	    }
	  }
	  Branch {
	    Points		    [0, 35]
	    Branch {
	      DstBlock		      "Multipath Rayleigh\nFading Channel2"
	      DstPort		      1
	    }
	    Branch {
	      Points		      [0, 125]
	      DstBlock		      "Multipath Rayleigh\nFading Channel3"
	      DstPort		      1
	    }
	  }
	}
      }
    }

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