v_blast.mdl
来自「v-blast的仿真」· MDL 代码 · 共 2,358 行 · 第 1/5 页
MDL
2,358 行
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskType "Replaced Block"
MaskDescription "This is a newly introduced block which was repl"
"aced with an empty Subsystem."
MaskDisplay "disp('Replaced: PermuteDimensions')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "Permute\nDimensions1"
Location [480, 93, 1016, 386]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [35, 23, 65, 37]
IconDisplay "Port number"
}
Block {
BlockType Ground
Name "Ground1"
Position [165, 20, 185, 40]
}
Block {
BlockType Terminator
Name "Terminator1"
Position [100, 20, 120, 40]
}
Block {
BlockType Outport
Name "Out1"
Position [250, 23, 280, 37]
IconDisplay "Port number"
}
Line {
SrcBlock "Ground1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Terminator1"
DstPort 1
}
}
}
Block {
BlockType Selector
Name "Selector"
Ports [1, 1]
Position [275, 31, 315, 69]
InputPortWidth "40"
InputType "Vector"
ElementSrc "Internal"
Elements "[1 5 9 13 17 21 25 29 33 37]"
RowSrc "Internal"
Rows "[1 5 9 13 17 21 25 29 33 37]"
ColumnSrc "Internal"
Columns "1"
IndexIsStartValue off
OutputPortSize "[(-2)]"
}
Block {
BlockType Selector
Name "Selector1"
Ports [1, 1]
Position [275, 136, 315, 174]
InputPortWidth "40"
InputType "Vector"
ElementSrc "Internal"
Elements "[2 6 10 14 18 22 26 30 34 38]"
RowSrc "Internal"
Rows "[2 6 10 14 18 22 26 30 34 38]"
ColumnSrc "Internal"
Columns "1"
IndexIsStartValue off
OutputPortSize "[(-2)]"
}
Block {
BlockType Selector
Name "Selector2"
Ports [1, 1]
Position [275, 236, 315, 274]
InputPortWidth "40"
InputType "Vector"
ElementSrc "Internal"
Elements "[3 7 11 15 19 23 27 31 35 39]"
RowSrc "Internal"
Rows "[3 7 11 15 19 23 27 31 35 39]"
ColumnSrc "Internal"
Columns "1"
IndexIsStartValue off
OutputPortSize "[(-2)]"
}
Block {
BlockType Selector
Name "Selector3"
Ports [1, 1]
Position [275, 346, 315, 384]
InputPortWidth "40"
InputType "Vector"
ElementSrc "Internal"
Elements "[4 8 12 16 20 24 28 32 36 40]"
RowSrc "Internal"
Rows "[4 8 12 16 20 24 28 32 36 40]"
ColumnSrc "Internal"
Columns "1"
IndexIsStartValue off
OutputPortSize "[(-2)]"
}
Block {
BlockType Selector
Name "Selector4"
Ports [1, 1]
Position [270, 436, 310, 474]
InputPortWidth "40"
InputType "Vector"
ElementSrc "Internal"
Elements "[1 5 9 13 17 21 25 29 33 37]"
RowSrc "Internal"
Rows "[1 5 9 13 17 21 25 29 33 37]"
ColumnSrc "Internal"
Columns "1"
IndexIsStartValue off
OutputPortSize "[(-2)]"
}
Block {
BlockType Selector
Name "Selector5"
Ports [1, 1]
Position [270, 541, 310, 579]
InputPortWidth "40"
InputType "Vector"
ElementSrc "Internal"
Elements "[2 6 10 14 18 22 26 30 34 38]"
RowSrc "Internal"
Rows "[2 6 10 14 18 22 26 30 34 38]"
ColumnSrc "Internal"
Columns "1"
IndexIsStartValue off
OutputPortSize "[(-2)]"
}
Block {
BlockType Selector
Name "Selector6"
Ports [1, 1]
Position [270, 641, 310, 679]
InputPortWidth "40"
InputType "Vector"
ElementSrc "Internal"
Elements "[3 7 11 15 19 23 27 31 35 39]"
RowSrc "Internal"
Rows "[3 7 11 15 19 23 27 31 35 39]"
ColumnSrc "Internal"
Columns "1"
IndexIsStartValue off
OutputPortSize "[(-2)]"
}
Block {
BlockType Selector
Name "Selector7"
Ports [1, 1]
Position [270, 751, 310, 789]
InputPortWidth "40"
InputType "Vector"
ElementSrc "Internal"
Elements "[4 8 12 16 20 24 28 32 36 40]"
RowSrc "Internal"
Rows "[4 8 12 16 20 24 28 32 36 40]"
ColumnSrc "Internal"
Columns "1"
IndexIsStartValue off
OutputPortSize "[(-2)]"
}
Block {
BlockType SubSystem
Name "Subsystem"
Ports [1, 4]
Position [355, 16, 395, 79]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Subsystem"
Location [2, 82, 1270, 753]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [90, 418, 120, 432]
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "AWGN\nChannel"
Ports [1, 1]
Position [640, 71, 735, 129]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "73"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "SNR"
EsNodB "10"
SNRdB "SNR"
bitsPerSym "1"
Ps "0.1"
Tsym "14e-5"
variance "1"
}
Block {
BlockType Reference
Name "AWGN\nChannel1"
Ports [1, 1]
Position [645, 176, 740, 234]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "730"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "SNR"
EsNodB "10"
SNRdB "SNR"
bitsPerSym "1"
Ps "0.1"
Tsym "14e-5"
variance "1"
}
Block {
BlockType Reference
Name "AWGN\nChannel2"
Ports [1, 1]
Position [650, 291, 745, 349]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "800"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "SNR"
EsNodB "10"
SNRdB "SNR"
bitsPerSym "1"
Ps "0.1"
Tsym "14e-5"
variance "1"
}
Block {
BlockType Reference
Name "AWGN\nChannel3"
Ports [1, 1]
Position [655, 416, 750, 474]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "900"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "SNR"
EsNodB "10"
SNRdB "SNR"
bitsPerSym "1"
Ps "0.1"
Tsym "14e-5"
variance "1"
}
Block {
BlockType Constant
Name "Constant"
Position [100, 130, 130, 160]
SampleTime "160e-5"
}
Block {
BlockType Constant
Name "Constant1"
Position [95, 200, 125, 230]
Value "0"
SampleTime "160e-5"
}
Block {
BlockType Constant
Name "Constant2"
Position [95, 270, 125, 300]
Value "0"
SampleTime "160e-5"
}
Block {
BlockType Constant
Name "Constant3"
Position [95, 340, 125, 370]
Value "0"
SampleTime "160e-5"
}
Block {
BlockType Reference
Name "Matrix\nConcatenate"
Ports [5, 1]
Position [260, 104, 345, 466]
SourceBlock "simulink/Math\nOperations/Matrix\nConcatenation"
SourceType "Matrix Concatenation"
numInports "5"
catMethod "Vertical"
}
Block {
BlockType Reference
Name "Multipath Rayleigh\nFading Channel"
Ports [1, 1]
Position [465, 71, 560, 129]
SourceBlock "commchan2/Multipath Rayleigh\nFading Channel"
SourceType "Multipath Rayleigh Fading Channel"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "73"
}
Block {
BlockType Reference
Name "Multipath Rayleigh\nFading Channel1"
Ports [1, 1]
Position [465, 176, 560, 234]
SourceBlock "commchan2/Multipath Rayleigh\nFading Channel"
SourceType "Multipath Rayleigh Fading Channel"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "730"
}
Block {
BlockType Reference
Name "Multipath Rayleigh\nFading Channel2"
Ports [1, 1]
Position [465, 291, 560, 349]
SourceBlock "commchan2/Multipath Rayleigh\nFading Channel"
SourceType "Multipath Rayleigh Fading Channel"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "800"
}
Block {
BlockType Reference
Name "Multipath Rayleigh\nFading Channel3"
Ports [1, 1]
Position [465, 416, 560, 474]
SourceBlock "commchan2/Multipath Rayleigh\nFading Channel"
SourceType "Multipath Rayleigh Fading Channel"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "900"
}
Block {
BlockType Outport
Name "Out1"
Position [880, 93, 910, 107]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out2"
Position [880, 198, 910, 212]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out3"
Position [875, 313, 905, 327]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out4"
Position [880, 438, 910, 452]
Port "4"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Matrix\nConcatenate"
DstPort 5
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Matrix\nConcatenate"
DstPort 1
}
Line {
SrcBlock "Constant1"
SrcPort 1
DstBlock "Matrix\nConcatenate"
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