amf_divider_s_render.asm

ADI SHARC DSP 音频算法标准模块库

// Copyright(c) 2005 Analog Devices, Inc. All Rights Reserved.
// This software is proprietary and confidential to Analog Devices, Inc. and its licensors.

// File    : $Id: //depot/development/visualaudio/modules/2.5.0/SHARC/Source/AMF_Divider_S_Render.asm#3 $ 
// Part of : VisualAudio V2.5.0 
// Updated : $Date: 2006/10/12 $ by $Author: Fernando $



//    Module Name     : AMF_Divider_S.asm 
//    DSP Processor   : ADSP21161
//    Original Author : Tim Stilson, based on code example in Sharc Instruction Set Reference
//    Date               : 1/12/04
//====================================================================================
// Processor resources used:
//    28 words pmem INTERNAL
//  793 cycles, tickSize=128, (25 + 6*tickSize)
//====================================================================================

//====================================================================================
// Discussion
//
// The math in this module is based on the code snippet in the RECIPS section of the
// 21160 Instruction Set Reference Manual (p 7-43).  The text there notes that if one only
// needs accuracy to +/- 1 LSB at 32-bit accuracy, that one of the successive-approximation
// iterations can be removed.  This module does have the iteration removed, so would
// not directly be a sufficient basis for a 40-bit module, in which case the removed
// iteration would need to be restored.
//
// NOTE: an informal experimental error analysis of the resulting divide seems to imply
// a worst case error closer to +/- 2 LSBs, though the vast majority of cases had error
// well within +/- 1 LSB.
//====================================================================================
 
#if 1
 
#include <processor.h>
#include "AMF_Divider_S.h"
#include "asm_sprt.h"

.global    _AMF_Divider_S_Render;            ;

.segment /pm SEG_MOD_FAST_CODE;
_AMF_Divider_S_Render:

//====================================================================================
    entry;   
    
//module entry arguments passed in registers: 
//  r4  = instance    (AMF_Divider_S * restrict)
//  r8  = * buffers (float * restrict)
//  r12 = int tickSize

    puts=mode1;
    r0=i0; puts=r0;
    r0=i1; puts=r0;

    r2 = r12;                    // ticksize

    m4=2;                        // SIMD loop increment
    
    i4=r8;                        //i4->*buffers
    bit set mode1 PEYEN;        // Enable PEy:SIMD

    i0=dm(0,i4);                // i0=float *in1
    i1=dm(1,i4);                // i1=float *in2
    i4=dm(2,i4);                // i4=float *out1

    f8 = 2.0;                    // f8/s8 = 2.0

        f4=dm(i0,m4);                                // f4 = in1[i++] (numerator)
        f12=dm(i1,m4);                                // f2 = in2[i++] (denom)
        f0=recips f12;                                 // Get first 8 bit seed R0=1/D
    LCNTR=r2, DO AMF_Divider_S_Render_loop_end UNTIL LCE;
        f12=f0*f12;                                 // D' = D*R0
        f4=f0*f4,      f0=f8-f12;                     // F0=R1=2-D', F4=N*R0    } repeat this pair of lines to
        f12=f0*f12;                                 // F12=D'-D'*R1         } get back to 40-bit accuracy
        f4=f0*f4,      f0=f8-f12,  f12=dm(i1,m4);     // F4=N*R0*R1, F0=R2=2-D', f12 = next denominator
        f0=f0*f4,                    f4 =dm(i0,m4);    // F0=N*R0*R1*R2, f4 = next numerator
AMF_Divider_S_Render_loop_end: 
        f0=recips f12,             dm(i4,m4)=f0;    // f0 = next seed, out[i++]=f0

    bit clr mode1 PEYEN;    // Disable PEy:SIMD
        
//====================================================================================

    i1=gets(1);
    i0=gets(2);
    mode1=gets(3);
    alter(3);

    
//------------------------------------------------------------------------------------
_AMF_Divider_S_Render.END:
    leaf_exit; // C-rth requires this instead of rts
//------------------------------------------------------------------------------------
.endseg;
#endif