amf_scl1add2_s_render.asm

ADI SHARC DSP 音频算法标准模块库

// Copyright(c) 2005 Analog Devices, Inc. All Rights Reserved.
// This software is proprietary and confidential to Analog Devices, Inc. and its licensors.

// File    : $Id: //depot/development/visualaudio/modules/2.5.0/SHARC/Source/AMF_Scl1Add2_S_Render.asm#3 $ 
// Part of : VisualAudio V2.5.0 
// Updated : $Date: 2006/10/12 $ by $Author: Fernando $



//    Module Name     : AMF_Scl1Add2_S.asm 
//    DSP Processor   : ADSP21161
//    Original Author : Sean Costello    
//    Date               : 2/19/04
//====================================================================================
// Processor resources used:
//    30 words pmem INTERNAL
// 411 cycles, tickSize=128 (27 + 3*tickSize)
//====================================================================================


#if 1

#include <processor.h>
#include "AMF_Scl1Add2_S.h"
#include "asm_macros.h"
#include "asm_sprt.h"

.global    _AMF_Scl1Add2_S_Render;            ;

.segment /pm SEG_MOD_FAST_CODE;
_AMF_Scl1Add2_S_Render:

//====================================================================================
    entry;   
    
//module entry arguments passed in registers: 
//  r4  = instance    (AMF_Scl1Add2_S * restrict)
//  r8  = * buffers (float * restrict)
//  r12 = int tickSize

    puts=mode1;
    r0=i0; puts=r0;
    r0=i1; puts=r0;
    
    m4=2;                        // SIMD loop increment
    
    i4=r4;                        // i4->instance
    
    f2=dm(AMF_Scl1Add2_S_Amp,i4);    // f2= float Amp = instance->amp
    s2=f2;
    
    i4=r8;                        // i4->*buffers
    bit set mode1 PEYEN;        // Enable PEy:SIMD

    i0=dm(0,i4);                // i0=float *in1
    i1=dm(1,i4);                // i1=float *in2
    i4=dm(2,i4);                // i4=float *out1

    f1=dm(i0,m4);                // f1=in1[0]
    f8=dm(i1,m4);                // f8=in2[0]     

                                
AMF_Scl1Add2_S_Render_loop_start:
    // for (i=0; i<2*tickSize; i++) 
    LCNTR=r12, DO AMF_Scl1Add2_S_Render_loop_end UNTIL LCE;
        f0=f1*f2, f1=dm(i0,m4);        // f0=in1*amp, f1=in1[i++]
        f4=f0+f8, f8=dm(i1,m4);        // f4=f0+in2, f8=in2[i++]
AMF_Scl1Add2_S_Render_loop_end: 
        dm(i4,m4)=f4;                // out[i++]=f4

    bit clr mode1 PEYEN;    // Disable PEy:SIMD
        
//====================================================================================

    i1=gets(1);
    i0=gets(2);
    mode1=gets(3);
    alter(3);

    
//------------------------------------------------------------------------------------
_AMF_Scl1Add2_S_Render.END:
    leaf_exit; // C-rth requires this instead of rts
//------------------------------------------------------------------------------------
.endseg;
#endif