amf_biquadcascade_ds_render.asm

ADI SHARC DSP 音频算法标准模块库

// Copyright(c) 2005 Analog Devices, Inc. All Rights Reserved.
// This software is proprietary and confidential to Analog Devices, Inc. and its licensors.

// File    : $Id: //depot/development/visualaudio/modules/2.5.0/SHARC/Source/AMF_BiquadCascade_DS_Render.asm#3 $ 
// Part of : VisualAudio V2.5.0 
// Updated : $Date: 2006/10/12 $ by $Author: Fernando $




//    Module Name     : AMF_BiquadCascade_DS_Render.asm 
//    DSP Processor   : ADSP21161
//    Original Author : GJO  Ported to VA by Tim Stilson    
//    Date               : 6/19/03
//====================================================================================
// Processor resources used:
//  78 words pmem INTERNAL
//  881 cycles for tickSize=128 (1 stage)
//  cycles = 101 + TickSize*2 + numSections*(14 + TickSize*4)
// (SIMD used)
//====================================================================================

#if 1

        /**************************************************************

        File Name:    CASCADE_BC.asm
                
        Date Modified:    05/22/00        GJO
                        05/25/00        GJO    Code verified on rev 0.1 Silicon
                        06/19/03        Tim Stilson, made C callable, ported to VA
                        06/19/03        Tim Stilson, swapped quads loop and samples loop to be more efficient for few-stages cases
                        08/15/03        Tim Stilson, a few small code-size optimizations
                        11/04/03        Tim Stilson, reworked state handling while fixing a bug with numSections>=3

        Calling/Return:
                    See AMF_BiquadCascade_DS.h for C function declaration

        ****************************************************************************/

#include "processor.h"
#include "AMF_BiquadCascade_DS.h"
#include <asm_sprt.h>

// global routines
.global    _AMF_BiquadCascade_DS_Render;            ;

.segment /pm SEG_MOD_FAST_CODE;

_AMF_BiquadCascade_DS_Render:

    puts = r10;
	puts = mode1;
    puts = r7;
    puts = r6;
    puts = r5;
    puts = r3;
    r0 = i1;    puts = r0;
    r0 = i3;    puts = r0;
    puts = i9;


    i4 = r4;                /* Read structure pointer */
    
    r1 = r12;               /* Read number of points */
    r1 = r1 - 1;            /* iter count for inner loop */


    r0 = dm(AMF_BiquadCascade_DS_Coefs,i4);
    i9 = r0;


    f4 = dm(AMF_BiquadCascade_DS_TotalAmp1,i4);
    s4 = dm(AMF_BiquadCascade_DS_TotalAmp2,i4);

    
    r0 = dm(AMF_BiquadCascade_DS_State,i4);    
    b13 = r0;        // we can assume i13 starts on b13 because we assume TickSize is always a multiple of 2

    r0 = dm(AMF_BiquadCascade_DS_NumSections,i4);
    
    i4=r8;                    // i4->*buffers
    
 // initialize input and output samples pointers
    i3=dm(0,i4);            // i3->buffers[0], input
    i1=dm(1,i4);            // i1->buffers[1], output

     
// do initial scaling loop
    bit set MODE1 RND32 | PEYEN;         /* alu, multiplier precision -> 1 cycle of latency before PEYEN */
    nop; // ******* POSSIBLE ASSEMBLER BUG?????????? putting this here caused the scaleLoop: instr to be assembled correctly **********
    m4 = 2;                                        /* stride = 2 for SIMD            */
    f3 = dm(i3,m4);
    lcntr = r12, do scaleLoop until lce;
        f2 = f3*f4, f3 = dm(i3,m4);
scaleLoop:        dm(i1,m4) = f2;


    // reset i/o pointers for filter
    i1=dm(1,i4);            // scale loop scaled into output buffer, so that is now the input

    bit set mode1 CBUFEN;                

    m12 = 2;
    l13 = 4;
    b12 = b13;
    l12 = l13;
        

    lcntr=r0, do quads until lce;
        // reset i/o pointers
        i3=i1;
        i4=i1;
        f4 = pm(i9,m12); // a2
        f5 = pm(i9,m12); // a1
        f6 = pm(i9,m12); // b2
        f7 = pm(i9,m12); // b1

                            f8=dm(i3,m4),                f2=pm(i12,m12);    /* get w(n-2) *//* load input sample */
            f12=f2*f4,                                      f3=pm(i12,m12); /* w(n-2)xa2, get w(n-1) */
            f12=f3*f5,         f8=f8+f12;                                    /* w(n-1)xa1, x(n)+(w(n-2)xa2) */ 
            f12=f2*f6,         f8=f8+f12,                     f2=f3;            /* w(n-2)xb2, w(n) = x(n)+w(n-1)xa1+w(n-2)xa2, f2 = next w(n-2) */
            f12=f3*f7,        f8=f8+f12,                    f3=f8;           /* w(n-1)xb1, w(n)+(w(n-2)xb2), f3 = next w(n-1) */
        
        lcntr=r1, do filtering until lce;
            f12=f2*f4,         f8=f8+f12,   f10=dm(i3,m4);                 /* w(n-2)xa2, out=w(n)+(w(n-2)xb2)+w(n-1)*b1, get input */
            f12=f3*f5,         f10=f10+f12, dm(i4,m4)=f8;                    /* w(n-1)xa1, x(n)+(w(n-2)xa2), write out */ 
            f12=f2*f6,         f8=f10+f12,                 f2=f3;            /* w(n-2)xb2, w(n) = x(n)+w(n-1)xa1+w(n-2)xa2, f2 = next w(n-2)*/
filtering:    f12=f3*f7,        f8=f8+f12,                     f3=f8;           /* w(n-1)xb1, w(n)+(w(n-2)xb2), f3 = next w(n-1) */

                            f8=f8+f12,                    pm(i12,m12)=f2; /* calc last y after dropping out of loop, write out state w(n-2) */
                                         dm(i4,m4)=f8,    pm(i12,m12)=f3; /* write last output, write out state w(n-1) */

        // point to next set of states
        r2 = b13;
        r3 = 4;
        r2 = r2 + r3;
        b13 = r2;
quads:    b12 = r2;

    bit clr mode1 PEYEN;                /* disable SIMD mode */
    nop;

    
    l12 = 0;
    l13 = 0;

    i9  = gets(1);
    i3  = gets(2);
    i1  = gets(3);
    r3  = gets(4);
    r5  = gets(5);
    r6  = gets(6);
    r7  = gets(7);
    mode1=gets(8);
    r10  = gets(9);
    alter(9);

//------------------------------------------------------------------------------------
_AMF_BiquadCascade_DS_Render.END:
    leaf_exit; // C-rth requires this instead of rts
//------------------------------------------------------------------------------------
    
.endseg;
#endif