📄 start_v2.lst
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579 ; 1 = 8 bit Multiplexed bus
580 ; 2 = 16 bit Demultiplexed bus
581 ; 3 = 16 bit Multiplexed bus
582 ; </h>
583 ;
584 ; <h> TCONCS0: Definitions for the Timing Configuration register
585 ; ==============================================================
586 ;
587 ; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
0003 588 _PHA0 EQU 3 ; 0 = 0 clock cycles /Dave/
589 ; : = :
A166 MACRO ASSEMBLER START_V2 04/06/2009 22:15:28 PAGE 11
590 ; 3 = 3 clock cycles
591 ;
592 ; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
0000 593 _PHB0 EQU 0 ; 0 = 1 clock cycle /Dave/
594 ; 1 = 2 clock cycles
595 ;
596 ; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
0000 597 _PHC0 EQU 0 ; 0 = 0 clock cycles /Dave/
598 ; : = :
599 ; 3 = 3 clock cycles
600 ;
601 ; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
0000 602 _PHD0 EQU 0 ; 0 = 0 clock cycles /Dave/
603 ; 1 = 1 clock cycle
604 ;
605 ; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
0009 606 _PHE0 EQU 9 ; 0 = 1 clock cycle /Dave/
607 ; : = :
608 ; 31 = 32 clock cycles
609 ;
610 ; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
0000 611 _RDPHF0 EQU 0 ; 0 = 0 clock cycles /Dave/
612 ; : = :
613 ; 3 = 3 clock cycles
614 ;
615 ; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
0003 616 _WRPHF0 EQU 3 ; 0 = 0 clock cycles /Dave/
617 ; : = :
618 ; 3 = 3 clock cycles
619 ;</h> </e>
620 ;
621 ; <e> Configure External Bus Behaviour for CS1 Area
622 ; =================================================
623 ;
624 ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
625 $SET (CONFIG_CS1 = 0) ; /Dave/
626 ;
627 ; <h>Definitions for Address Select register ADDRSEL1
628 ; ===================================================
629 ; <o> CS1 Start Address <0x0-0xFFFFFF:0x1000>
0000 630 _ADDR1 EQU 0x0 ; Set CS1# Start Address (default 100000H) /Dave/
631
632 ; <o> CS1 Size in KB
633 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
634 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
635 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
1000 636 _SIZE1 EQU 4*KB ; Set CS1# Size (default 1024*KB = 1*MB) /Dave/
637 ; possible values for _SIZE1 are:
638 ; 4*KB (gives RGSZ1 = 0)
639 ; 8*KB (gives RGSZ1 = 1)
640 ; 16*KB (gives RGSZ1 = 2)
641 ; 32*KB (gives RGSZ1 = 3)
642 ; 64*KB (gives RGSZ1 = 4)
643 ; 128*KB (gives RGSZ1 = 5)
644 ; 256*KB (gives RGSZ1 = 6)
645 ; 512*KB (gives RGSZ1 = 7)
646 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
647 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
648 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
649 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
650 ; (RGSZ1 = 12 .. 15 reserved)
651 ;</h>
652 ;
653 ; <h>Definitions for Function Configuration Register FCONCS1
A166 MACRO ASSEMBLER START_V2 04/06/2009 22:15:28 PAGE 12
654 ; =======================================================
655 ;
656 ; <q> ENCS1: Enable Chip Select (FCONCS1.0)
0000 657 _ENCS1 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
658 ; 1 = Chip Select 0 enabled
659 ;
660 ; <q> RDYEN1: Ready Enable (FCONCS1.1)
0000 661 _RDYEN1 EQU 0 ; 0 = Access time controlled by TCONCS1.PHE1 /Dave/
662 ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
663 ;
664 ; <o> RDYMOD1: Ready Mode (FCONCS1.2)
665 ; <0=> Asynchronous <1=> Synchronous
0000 666 _RDYMOD1 EQU 0 ; 0 = Asynchronous READY /Dave/
667 ; 1 = Synchronous READY
668 ;
669 ; <o> BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
670 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
671 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0000 672 _BTYP1 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
673 ; 1 = 8 bit Multiplexed bus
674 ; 2 = 16 bit Demultiplexed bus
675 ; 3 = 16 bit Multiplexed bus
676 ;</h>
677 ;
678 ; <h>TCONCS1: Definitions for the Timing Configuration register
679 ; ==========================================================
680 ;
681 ; <o>PHA1: Phase A clock cycles (TCONCS1.0 .. TCONCS1.1) <0-3>
0000 682 _PHA1 EQU 0 ; 0 = 0 clock cycles /Dave/
683 ; : = :
684 ; 3 = 3 clock cycles
685 ;
686 ; <o>PHB1: Phase B clock cycles (TCONCS1.2) <1-2> <#-1>
0000 687 _PHB1 EQU 0 ; 0 = 1 clock cycle /Dave/
688 ; 1 = 2 clock cycles
689 ;
690 ; <o>PHC1: Phase C clock cycles (TCONCS1.3 .. TCONCS1.4) <0-3>
0000 691 _PHC1 EQU 0 ; 0 = 0 clock cycles /Dave/
692 ; : = :
693 ; 3 = 3 clock cycles
694 ;
695 ; <o>PHD1: Phase D clock cycles (TCONCS1.5) <0-1>
0000 696 _PHD1 EQU 0 ; 0 = 0 clock cycles /Dave/
697 ; 1 = 1 clock cycle
698 ;
699 ; <o> PHE1: Phase E clock cycles (TCONCS1.6 .. TCONCS1.10) <1-32> <#-1>
0000 700 _PHE1 EQU 0 ; 0 = 1 clock cycle /Dave/
701 ; : = :
702 ; 31 = 32 clock cycles
703 ;
704 ; <o>RDPHF1: Phase F read clock cycles (TCONCS1.11 .. TCONCS1.12) <0-3>
0000 705 _RDPHF1 EQU 0 ; 0 = 0 clock cycles /Dave/
706 ; : = :
707 ; 3 = 3 clock cycles
708 ;
709 ; <o>WRPHF1: Phase F write clock cycles (TCONCS1.13 .. TCONCS1.14) <0-3>
0000 710 _WRPHF1 EQU 0 ; 0 = 0 clock cycles /Dave/
711 ; : = :
712 ; 3 = 3 clock cycles
713 ;</h> </e>
714 ;
715 ;<e>Configure External Bus Behaviour for CS2 Area
A166 MACRO ASSEMBLER START_V2 04/06/2009 22:15:28 PAGE 13
716 ; =============================================
717 ;
718 ; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
719 $SET (CONFIG_CS2 = 0) ; /Dave/
720 ;
721 ; <h>Definitions for Address Select register ADDRSEL2
722 ; ===================================================
723 ; <o> CS2 Start Address <0x0-0xFFFFFF:0x1000>
0000 724 _ADDR2 EQU 0x0 ; Set CS2# Start Address (default 100000H) /Dave/
725
726 ; <o> CS2 Size in KB
727 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
728 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
729 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
1000 730 _SIZE2 EQU 4*KB ; Set CS2# Size (default 1024*KB = 1*MB) /Dave/
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