📄 start_v2.lst
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300 ;<q> Disable Timer Block GPT
0000 301 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3) /Dave/
302 ; reserved (SYSCON3.4)
A166 MACRO ASSEMBLER START_V2 04/06/2009 22:15:28 PAGE 6
303 ;<q> Disable on-chip Flash Memory Module
0000 304 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5) /Dave/
305 ;<q> Disable CAPCOM Unit 1
0001 306 CC1DIS EQU 1 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6) /Dave/
307 ;<q> Disable CAPCOM Unit 2
0001 308 CC2DIS EQU 1 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7) /Dave/
309 ;<q> Disable CAPCOM Unit 6
0001 310 CC6DIS EQU 1 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8) /Dave/
311 ; reserved (SYSCON3.9)
312 ;<q> Disable UART ASC1
0001 313 ASC1DIS EQU 1 ; 1 = disable UART ASC1 (SYSCON3.10) /Dave/
314 ;<q> Disable I2C Bus Module
0000 315 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11) /Dave/
316 ;<q> Disable SDLM (J1850) Module
0000 317 SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module (SYSCON3.12) /Dave/
318 ;<q> Disable on-chip CAN Module
0000 319 CANDIS EQU 0 ; 1 = disable on-chip CAN Module (SYSCON3.13) /Dave/
320 ;<q> Disable Real Time Clock
0000 321 RTCDIS EQU 0 ; 1 = disable Real Time Clock (SYSCON3.14)
322 ;<q> Disable Synchronus Serial Cnl1 SSC1
0001 323 SSC1DIS EQU 1 ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15) /Dave/
324 ;
325 ;</e>
326 ;</h>
327 ; <e> Definitions for Reset Configuration Register RSTCON
328 ; =======================================================
329 ;
330 ; INIT_RSTCON: Init RSTCON register
331 ; --- Set INIT_RSTCON = 0 to initilize the RSTCON register
332 $SET (INIT_RSTCON = 0) ; /Dave/
333 ;
334 ; <o> RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
335 ; <0=> 2 CPU clocks <1=> 4 CPU clocks <2=> 8 CPU clocks <3=> 16 CPU clocks
336 ; <4=> 32 CPU clocks <5=> 64 CPU clocks <6=> 128 CPU clocks <7=> 256 CPU clocks
0000 337 _RSTLEN EQU 0 ; 0 = 2 t_CPU clocks (default) /Dave/
338 ; 1 = 4 t_CPU clocks
339 ; 2 = 8 t_CPU clocks
340 ; 3 = 16 t_CPU clocks
341 ; 4 = 32 t_CPU clocks
342 ; 5 = 64 t_CPU clocks
343 ; 6 = 128 t_CPU clocks
344 ; 7 = 256 t_CPU clocks
345 ;
346 ; <o> RORMV: RSTOUT# Remove Control (RSTCON.4)
347 ; <0=> RSTOUT delivers RSTOUT# signal <1=> RSTOUT pin operates as GPIO
0000 348 _RORMV EQU 0 ; 0 = RSTOUT delivers RSTOUT# signal /Dave/
349 ; 1 = RSTOUT pin operates as GPIO
350 ;
351 ; <o> ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
352 ; <0=>RSTOUT deactivated by user software <1=>RSTOUT deactivated after reset
0000 353 _ROCOFF EQU 0 ; 0 = RSTOUT is deactivated by user software /Dave/
354 ; 1 = RSTOUT is deactivated at end of reset
355 ;
356 ; <o> ROCON: RSTOUT# Control Switch Off (RSTCON.6)
A166 MACRO ASSEMBLER START_V2 04/06/2009 22:15:28 PAGE 7
357 ; <0=> RSTOUT active on any reset <1=> RSTOUT active on hardware reset
0000 358 _ROCON EQU 0 ; 0 = RSTOUT is activated upon any reset /Dave/
359 ; 1 = RSTOUT is only activated upon a hardware reset
360 ;
361 ; <q> RODIS: RSTOUT# Disable Control (RSTCON.7) <0-1>
0000 362 _RODIS EQU 0 ; 0 = RSTOUT is controlled by other mechanism /Dave/
363 ; 1 = RSTOUT is deactivated
364 ;
365 ;</e>
366 ;
367 ;
368 ; <e> Definitions for PLL Control Register PLLCON
369 ; ===============================================
370 ;
371 ; INIT_PLLCON: Init PLLCON register
372 ; --- Set INIT_PLLCON = 0 to initilize the PLLCON register
373 $SET (INIT_PLLCON = 1) ; /Dave/
374 ;
375 ; <o> PLLODIV: PLL Output Divider (PLLCON.0 .. PLLCON.3) <0-14>
0004 376 _PLLODIV EQU 4 ; 0 .. 14 Fpll = Fvco / (PLLODIV+1) /Dave/
377 ; 15 = reserved
378 ;
379 ; <o> PLLIDIV: PLL Input Divider (PLLCON.4 .. PLLCON.5) <0-3>
380 ; <i> Fin = Fosc / (PLLIDIV+1)
0001 381 _PLLIDIV EQU 1 ; 0 .. 3 Fin = Fosc / (PLLIDIV+1) /Dave/
382 ;
383 ; <o> PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
384 ; <0=> Ouput:100-150MHz / Base:20-80MHz <1=> Ouput:150-200MHz / Base:40-130MHz
385 ; <2=> Ouput:200-250MHz / Base:60-180MHz <3=> (250...300 MHz) Reserved
0000 386 _PLLVB EQU 0 ; ValueVCO output frequency Base frequency /Dave/
387 ; 0 = 100...150 MHz 20...80 MHz
388 ; 1 = 150...200 MHz 40...130 MHz
389 ; 2 = 200...250 MHz [def.] 60...180 MHz
390 ; 3 = (250...300 MHz) Reserved
391 ;
392 ; <o> PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12) <6-31>
393 ; <i> Fvco = Fin * (PLLMUL+1)
0018 394 _PLLMUL EQU 24 ; 7 .. 31 Fvco = Fin * (PLLMUL+1) /Dave/
395 ; 0 .. 6 = reserved
396 ;
397 ; <o> PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
398 ; <0=> Bypass PLL clock mult., the VCO is off <1=> Bypass PLL clock mult., the VCO i
s running
399 ; <2=> VCO clock used, input clock switched off <3=> VCO clock used, input clock conne
cted
0003 400 _PLLCTRL EQU 3 ; 0 = Bypass PLL clock mult., the VCO is off /Dave/
401 ; 1 = Bypass PLL clock mult., the VCO is running
402 ; 2 = VCO clock used, input clock switched off
403 ; 3 = VCO clock used, input clock connected
404 ;
405 ; <o> PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
406 ; <0=> Register PLLCON may be written <1=> Write cycles to register PLLCON are ignore
d
0000 407 _PLLWRI EQU 0 ; 0 = Register PLLCON may be written
408 ; 1 = Write cycles to register PLLCON are ignored
409 ;</e>
410 ;
411 ; <e> Definitions for Watchdog Timer Control Register WDTCON
412 ; ==========================================================
A166 MACRO ASSEMBLER START_V2 04/06/2009 22:15:28 PAGE 8
413 ;
414 ; --- Set WATCHDOG = 0 to enable the Hardware watchdog and initilize the WDTCON regist
er
415 $SET (WATCHDOG = 0) ; 0 = Disabled Hardware watchdog /Dave/
416 ;
417 ; <o> WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
418 ; <0=> Peripheral Frequency divided by 2 <1=> Peripheral Frequency divided by 128
419 ; <2=> Peripheral Frequency divided by 4 <3=> Peripheral Frequency divided by 256
0000 420 _WDTIN EQU 0 ; 0 = frequency f_peripheral / 2 (CPU default) /Dave/
421 ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
422 ; 2 = frequency f_peripheral / 4
423 ; 3 = frequency f_peripheral / 256
424 ;
425 ; <o> WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15) <0-255>
426 ; <i> High byte of WDT (counts up, overflow gives Watchdog reset)
0000 427 _WDTREL EQU 0 ; /Dave/
428 ;
429 ;</e>
430 ; <e> Definitions for Frequency Output Signal FOCON
431 ; =================================================
432 ;
433 ; INIT_FOCON: Init FOCON register
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