📄 start_v2.a66
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;
; --- Set CONFIG_CS3 = 1 to initialize the ADDRSEL3/FCONCS3/TCONCS3 registers
$SET (CONFIG_CS3 = 0) ; /Dave/
;
; <h>Definitions for Address Select register ADDRSEL3
; ===================================================
; <o> CS3 Start Address <0x0-0xFFFFFF:0x1000>
_ADDR3 EQU 0x0 ; Set CS3# Start Address (default 100000H) /Dave/
; <o> CS2 Size in KB
; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
_SIZE3 EQU 4*KB ; Set CS3# Size (default 1024*KB = 1*MB) /Dave/
; possible values for _SIZE3 are:
; 4*KB (gives RGSZ3 = 0)
; 8*KB (gives RGSZ3 = 1)
; 16*KB (gives RGSZ3 = 2)
; 32*KB (gives RGSZ3 = 3)
; 64*KB (gives RGSZ3 = 4)
; 128*KB (gives RGSZ3 = 5)
; 256*KB (gives RGSZ3 = 6)
; 512*KB (gives RGSZ3 = 7)
; 1024*KB or 1*MB (gives RGSZ3 = 8)
; 2048*KB or 2*MB (gives RGSZ3 = 9)
; 4096*KB or 4*MB (gives RGSZ3 = 10)
; 8192*KB or 8*MB (gives RGSZ3 = 11)
; (RGSZ3 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS3
; =======================================================
;
; <q> ENCS3: Enable Chip Select (FCONCS3.0)
_ENCS3 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
; 1 = Chip Select 0 enabled
;
; <q> RDYEN3: Ready Enable (FCONCS3.1)
_RDYEN3 EQU 0 ; 0 = Access time controlled by TCONCS3.PHE1 /Dave/
; 1 = Access time cont. by TCONCS3.PHE1 and READY signal
;
; <o> RDYMOD3: Ready Mode (FCONCS3.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD3 EQU 0 ; 0 = Asynchronous READY /Dave/
; 1 = Synchronous READY
;
; <o> BTYP3 Bus Type Selection (FCONCS3.4 .. FCONCS3.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP3 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;</h>
;
; <h>TCONCS2: Definitions for the Timing Configuration register
; ==========================================================
;
; <o>PHA3: Phase A clock cycle (TCONCS3.0 .. TCONCS3.1) <0-3>
_PHA3 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHB3: Phase B clock cycle (TCONCS2.2) <1-2> <#-1>
_PHB3 EQU 0 ; 0 = 1 clock cycle /Dave/
; 1 = 2 clock cycles
;
; <o>PHC3: Phase C clock cycle (TCONCS3.3 .. TCONCS3.4) <0-3>
_PHC3 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHD3: Phase D clock cycle (TCONCS3.5) <0-1>
_PHD3 EQU 0 ; 0 = 0 clock cycles /Dave/
; 1 = 1 clock cycle
;
; <o> PHE3: Phase E clock cycle (TCONCS3.6 .. TCONCS3.10) <1-32> <#-1>
_PHE3 EQU 0 ; 0 = 1 clock cycle /Dave/
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF3: Phase F read clock cycle (TCONCS3.11 .. TCONCS3.12) <0-3>
_RDPHF3 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>WRPHF3: Phase F write clock cycle (TCONCS3.13 .. TCONCS3.14) <0-3>
_WRPHF3 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;</h> </e>
;
;<e>Configure External Bus Behaviour for CS4 Area
; =============================================
;
; --- Set CONFIG_CS4 = 1 to initialize the ADDRSEL4/FCONCS4/TCONCS4 registers
$SET (CONFIG_CS4 = 0) ; /Dave/
;
; <h>Definitions for Address Select register ADDRSEL4
; ===================================================
; <o> CS4 Start Address <0x0-0xFFFFFF:0x1000>
_ADDR4 EQU 0x0 ; Set CS4# Start Address (default 100000H) /Dave/
; <o> CS4 Size in KB
; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
_SIZE4 EQU 4*KB ; Set CS4# Size (default 1024*KB = 1*MB) /Dave/
; possible values for _SIZE4 are:
; 4*KB (gives RGSZ4 = 0)
; 8*KB (gives RGSZ4 = 1)
; 16*KB (gives RGSZ4 = 2)
; 32*KB (gives RGSZ4 = 3)
; 64*KB (gives RGSZ4 = 4)
; 128*KB (gives RGSZ4 = 5)
; 256*KB (gives RGSZ4 = 6)
; 512*KB (gives RGSZ4 = 7)
; 1024*KB or 1*MB (gives RGSZ4 = 8)
; 2048*KB or 2*MB (gives RGSZ4 = 9)
; 4096*KB or 4*MB (gives RGSZ4 = 10)
; 8192*KB or 8*MB (gives RGSZ4 = 11)
; (RGSZ4 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS4
; =======================================================
;
; <q> ENCS4: Enable Chip Select (FCONCS4.0)
_ENCS4 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
; 1 = Chip Select 0 enabled
;
; <q> RDYEN4: Ready Enable (FCONCS4.1)
_RDYEN4 EQU 0 ; 0 = Access time controlled by TCONCS4.PHE1 /Dave/
; 1 = Access time cont. by TCONCS4.PHE1 and READY signal
;
; <o> RDYMOD4: Ready Mode (FCONCS4.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD4 EQU 0 ; 0 = Asynchronous READY /Dave/
; 1 = Synchronous READY
;
; <o> BTYP4: Bus Type Selection (FCONCS4.4 .. FCONCS4.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP4 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;</h>
;
; <h>TCONCS4: Definitions for the Timing Configuration register
; ==========================================================
;
; <o>PHA4: Phase A clock cycle (TCONCS4.0 .. TCONCS4.1) <0-3>
_PHA4 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHB4: Phase B clock cycle (TCONCS4.2) <1-2> <#-1>
_PHB4 EQU 0 ; 0 = 1 clock cycle /Dave/
; 1 = 2 clock cycles
;
; <o>PHC4: Phase C clock cycle (TCONCS4.3 .. TCONCS4.4) <0-3>
_PHC4 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHD4: Phase D clock cycle (TCONCS4.5) <0-1>
_PHD4 EQU 0 ; 0 = 0 clock cycles /Dave/
; 1 = 1 clock cycle
;
; <o> PHE4: Phase E clock cycle (TCONCS4.6 .. TCONCS4.10) <1-32> <#-1>
_PHE4 EQU 0 ; 0 = 1 clock cycle /Dave/
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF4: Phase F read clock cycle (TCONCS4.11 .. TCONCS4.12) <0-3>
_RDPHF4 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>WRPHF4: Phase F write clock cycle (TCONCS4.13 .. TCONCS4.14) <0-3>
_WRPHF4 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;</h> </e>
;
;<e>Configure External Bus Behaviour for CS5 Area
; =============================================
;
; --- Set CONFIG_CS5 = 1 to initialize the ADDRSEL5/FCONCS5/TCONCS5 registers
$SET (CONFIG_CS5 = 0) ; /Dave/
;
; <h>Definitions for Address Select register ADDRSEL5
; ===================================================
; <o> CS5 Start Address <0x0-0xFFFFFF:0x1000>
_ADDR5 EQU 0x0 ; Set CS5# Start Address (default 100000H) /Dave/
; <o> CS5 Size in KB
; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
_SIZE5 EQU 4*KB ; Set CS5# Size (default 1024*KB = 1*MB) /Dave/
; possible values for _SIZE5 are:
; 4*KB (gives RGSZ5 = 0)
; 8*KB (gives RGSZ5 = 1)
; 16*KB (gives RGSZ5 = 2)
; 32*KB (gives RGSZ5 = 3)
; 64*KB (gives RGSZ5 = 4)
; 128*KB (gives RGSZ5 = 5)
; 256*KB (gives RGSZ5 = 6)
; 512*KB (gives RGSZ5 = 7)
; 1024*KB or 1*MB (gives RGSZ5 = 8)
; 2048*KB or 2*MB (gives RGSZ5 = 9)
; 4096*KB or 4*MB (gives RGSZ5 = 10)
; 8192*KB or 8*MB (gives RGSZ5 = 11)
; (RGSZ5 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS5
; =======================================================
;
; <q> ENCS5: Enable Chip Select (FCONCS5.0)
_ENCS5 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
; 1 = Chip Select 0 enabled
;
; <q> RDYEN5: Ready Enable (FCONCS5.1)
_RDYEN5 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE1 /Dave/
; 1 = Access time cont. by TCONCS2.PHE1 and READY signal
;
; <o> RDYMOD2: Ready Mode (FCONCS5.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD5 EQU 0 ; 0 = Asynchronous READY /Dave/
; 1 = Synchronous READY
;
; <o> BTYP2: Bus Type Selection (FCONCS5.4 .. FCONCS5.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP5 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;</h>
;
; <h>TCONCS5: Definitions for the Timing Configuration register
; ==========================================================
;
; <o>PHA5: Phase A clock cycle (TCONCS5.0 .. TCONCS5.1) <0-3>
_PHA5 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHB5: Phase B clock cycle (TCONCS5.2) <1-2> <#-1>
_PHB5 EQU 0 ; 0 = 1 clock cycle /Dave/
; 1 = 2 clock cycles
;
; <o>PHC5: Phase C clock cycle (TCONCS5.3 .. TCONCS5.4) <0-3>
_PHC5 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHD5: Phase D clock cycle (TCONCS5.5) <0-1>
_PHD5 EQU 0 ; 0 = 0 clock cycles /Dave/
; 1 = 1 clock cycle
;
; <o> PHE5: Phase E clock cycle (TCONCS5.6 .. TCONCS5.10) <1-32> <#-1>
_PHE5 EQU 0 ; 0 = 1 clock cycle /Dave/
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF5: Phase F read clock cycle (TCONCS5.11 .. TCONCS5.12) <0-3>
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