📄 start_v2.a66
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; 1 = Address bus pin 7-0 of PORT1 disabled
;
; <q> DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
_DHPDIS EQU 1 ; 0 = Data bus pins 15-8 of PORT0 enabled /Dave/
; 1 = Data bus pins 15-8 disabled (used as GPIO)
;
; <q> WRPDIS: WR/WRL Pin Disable (EBCMOD1.7)
_WRPDIS EQU 0 ; 0 = WR/WRL pin of Port P20 enabled /Dave/
; 1 = WR/WRL pin of Port P20 disabled
;
;</h></e>
;
; <e> Configure External Bus Behaviour for CS0 area
; =================================================
;
; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
$SET (CONFIG_CS0 = 1) ; /Dave/
;
; <h>Definitions for Function Configuration Register FCONCS0
; =======================================================
;
; <q> ENCS0: Enable Chip Select (FCONCS0.0)
_ENCS0 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
; 1 = Chip Select 0 enabled
;
; <q> RDYEN0: Ready Enable (FCONCS0.1)
_RDYEN0 EQU 0 ; 0 = Access time controlled by TCONCS0.PHE0 /Dave/
; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
;
; <o> RDYMOD0: Ready Mode (FCONCS0.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD0 EQU 0 ; 0 = Asynchronous READY /Dave/
; 1 = Synchronous READY
;
; <o> BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP0 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
; </h>
;
; <h> TCONCS0: Definitions for the Timing Configuration register
; ==============================================================
;
; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
_PHA0 EQU 3 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
_PHB0 EQU 0 ; 0 = 1 clock cycle /Dave/
; 1 = 2 clock cycles
;
; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
_PHC0 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
_PHD0 EQU 0 ; 0 = 0 clock cycles /Dave/
; 1 = 1 clock cycle
;
; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
_PHE0 EQU 9 ; 0 = 1 clock cycle /Dave/
; : = :
; 31 = 32 clock cycles
;
; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
_RDPHF0 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
_WRPHF0 EQU 3 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;</h> </e>
;
; <e> Configure External Bus Behaviour for CS1 Area
; =================================================
;
; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
$SET (CONFIG_CS1 = 0) ; /Dave/
;
; <h>Definitions for Address Select register ADDRSEL1
; ===================================================
; <o> CS1 Start Address <0x0-0xFFFFFF:0x1000>
_ADDR1 EQU 0x0 ; Set CS1# Start Address (default 100000H) /Dave/
; <o> CS1 Size in KB
; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
_SIZE1 EQU 4*KB ; Set CS1# Size (default 1024*KB = 1*MB) /Dave/
; possible values for _SIZE1 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS1
; =======================================================
;
; <q> ENCS1: Enable Chip Select (FCONCS1.0)
_ENCS1 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
; 1 = Chip Select 0 enabled
;
; <q> RDYEN1: Ready Enable (FCONCS1.1)
_RDYEN1 EQU 0 ; 0 = Access time controlled by TCONCS1.PHE1 /Dave/
; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
;
; <o> RDYMOD1: Ready Mode (FCONCS1.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD1 EQU 0 ; 0 = Asynchronous READY /Dave/
; 1 = Synchronous READY
;
; <o> BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP1 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;</h>
;
; <h>TCONCS1: Definitions for the Timing Configuration register
; ==========================================================
;
; <o>PHA1: Phase A clock cycles (TCONCS1.0 .. TCONCS1.1) <0-3>
_PHA1 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHB1: Phase B clock cycles (TCONCS1.2) <1-2> <#-1>
_PHB1 EQU 0 ; 0 = 1 clock cycle /Dave/
; 1 = 2 clock cycles
;
; <o>PHC1: Phase C clock cycles (TCONCS1.3 .. TCONCS1.4) <0-3>
_PHC1 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHD1: Phase D clock cycles (TCONCS1.5) <0-1>
_PHD1 EQU 0 ; 0 = 0 clock cycles /Dave/
; 1 = 1 clock cycle
;
; <o> PHE1: Phase E clock cycles (TCONCS1.6 .. TCONCS1.10) <1-32> <#-1>
_PHE1 EQU 0 ; 0 = 1 clock cycle /Dave/
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF1: Phase F read clock cycles (TCONCS1.11 .. TCONCS1.12) <0-3>
_RDPHF1 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>WRPHF1: Phase F write clock cycles (TCONCS1.13 .. TCONCS1.14) <0-3>
_WRPHF1 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;</h> </e>
;
;<e>Configure External Bus Behaviour for CS2 Area
; =============================================
;
; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
$SET (CONFIG_CS2 = 0) ; /Dave/
;
; <h>Definitions for Address Select register ADDRSEL2
; ===================================================
; <o> CS2 Start Address <0x0-0xFFFFFF:0x1000>
_ADDR2 EQU 0x0 ; Set CS2# Start Address (default 100000H) /Dave/
; <o> CS2 Size in KB
; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
_SIZE2 EQU 4*KB ; Set CS2# Size (default 1024*KB = 1*MB) /Dave/
; possible values for _SIZE2 are:
; 4*KB (gives RGSZ2 = 0)
; 8*KB (gives RGSZ2 = 1)
; 16*KB (gives RGSZ2 = 2)
; 32*KB (gives RGSZ2 = 3)
; 64*KB (gives RGSZ2 = 4)
; 128*KB (gives RGSZ2 = 5)
; 256*KB (gives RGSZ2 = 6)
; 512*KB (gives RGSZ2 = 7)
; 1024*KB or 1*MB (gives RGSZ2 = 8)
; 2048*KB or 2*MB (gives RGSZ2 = 9)
; 4096*KB or 4*MB (gives RGSZ2 = 10)
; 8192*KB or 8*MB (gives RGSZ2 = 11)
; (RGSZ2 = 12 .. 15 reserved)
;</h>
;
; <h>Definitions for Function Configuration Register FCONCS2
; =======================================================
;
; <q> ENCS2: Enable Chip Select (FCONCS2.0)
_ENCS2 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
; 1 = Chip Select 0 enabled
;
; <q> RDYEN2: Ready Enable (FCONCS2.1)
_RDYEN2 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE1 /Dave/
; 1 = Access time cont. by TCONCS2.PHE1 and READY signal
;
; <o> RDYMOD2: Ready Mode (FCONCS2.2)
; <0=> Asynchronous <1=> Synchronous
_RDYMOD2 EQU 0 ; 0 = Asynchronous READY /Dave/
; 1 = Synchronous READY
;
; <o> BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
_BTYP2 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;</h>
;
; <h>TCONCS2: Definitions for the Timing Configuration register
; ==========================================================
;
; <o>PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1) <0-3>
_PHA2 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHB2: Phase B clock cycle (TCONCS2.2) <1-2> <#-1>
_PHB2 EQU 0 ; 0 = 1 clock cycle /Dave/
; 1 = 2 clock cycles
;
; <o>PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4) <0-3>
_PHC2 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>PHD2: Phase D clock cycle (TCONCS2.5) <0-1>
_PHD2 EQU 0 ; 0 = 0 clock cycles /Dave/
; 1 = 1 clock cycle
;
; <o> PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10) <1-32> <#-1>
_PHE2 EQU 0 ; 0 = 1 clock cycle /Dave/
; : = :
; 31 = 32 clock cycles
;
; <o>RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12) <0-3>
_RDPHF2 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;
; <o>WRPHF2: Phase F write clock cycle (TCONCS2.13 .. TCONCS2.14) <0-3>
_WRPHF2 EQU 0 ; 0 = 0 clock cycles /Dave/
; : = :
; 3 = 3 clock cycles
;</h> </e>
;
;<e>Configure External Bus Behaviour for CS3 Area
; =============================================
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