📄 at91sam7a3.h
字号:
#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area
#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals
#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register
#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register
#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register
#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register
#endif
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status
#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection
#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access
#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access
#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only
#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write
#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size
#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte
#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte
#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte
#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte
#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte
#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte
#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte
#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte
#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte
#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte
#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte
#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte
#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte
#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte
#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte
#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte
#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address
// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_EOP (0x1 << 0) // (MC) End Of Programming Flag
#define AT91C_MC_EOL (0x1 << 1) // (MC) End Of Lock/Unlock Flag
#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error Flag
#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error Flag
#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Status Register --------
#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CAN_MB {
AT91_REG CAN_MB_MMR; // MailBox Mode Register
AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
AT91_REG CAN_MB_MID; // MailBox ID Register
AT91_REG CAN_MB_MFID; // MailBox Family ID Register
AT91_REG CAN_MB_MSR; // MailBox Status Register
AT91_REG CAN_MB_MDL; // MailBox Data Low Register
AT91_REG CAN_MB_MDH; // MailBox Data High Register
AT91_REG CAN_MB_MCR; // MailBox Control Register
} AT91S_CAN_MB, *AT91PS_CAN_MB;
#else
#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register
#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register
#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register
#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register
#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register
#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register
#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register
#endif
// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_CAN {
AT91_REG CAN_MR; // Mode Register
AT91_REG CAN_IER; // Interrupt Enable Register
AT91_REG CAN_IDR; // Interrupt Disable Register
AT91_REG CAN_IMR; // Interrupt Mask Register
AT91_REG CAN_SR; // Status Register
AT91_REG CAN_BR; // Baudrate Register
AT91_REG CAN_TIM; // Timer Register
AT91_REG CAN_TIMESTP; // Time Stamp Register
AT91_REG CAN_ECR; // Error Counter Register
AT91_REG CAN_TCR; // Transfer Command Register
AT91_REG CAN_ACR; // Abort Command Register
AT91_REG Reserved0[52]; //
AT91_REG CAN_VR; // Version Register
AT91_REG Reserved1[64]; //
AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
} AT91S_CAN, *AT91PS_CAN;
#else
#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register
#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register
#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register
#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register
#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register
#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register
#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register
#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register
#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register
#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register
#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register
#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register
#endif
// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of ⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -