📄 c8051f040.h
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sfr PCA0CPL3 = 0xEB; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH3 = 0xEC; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
sfr PCA0CPL4 = 0xED; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH4 = 0xEE; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
sfr RSTSRC = 0xEF; /* RESET SOURCE */
sfr B = 0xF0; /* B REGISTER */
sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
sfr SPI0CN = 0xF8; /* SPI 0 CONTROL */
sfr CAN0CN = 0xF8; /* CAN 0 CONTROL */
sfr P7 = 0xF8; /* PORT 7 */
sfr PCA0L = 0xF9; /* PCA 0 TIMER - LOW BYTE */
sfr PCA0H = 0xFA; /* PCA 0 TIMER - HIGH BYTE */
sfr PCA0CPL0 = 0xFB; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH0 = 0xFC; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
sfr PCA0CPL1 = 0xFD; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
sfr PCA0CPH1 = 0xFE; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
sfr16 ADC0DATA = 0xBE;
/**************************************/
/* BIT Registers */
/**************************************/
/**************************************/
/* TCON 0x88 */
/**************************************/
sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
/**************************************/
/* CPT0CN 0x88 */
/**************************************/
sbit CP0EN = CPT0CN ^ 7; /* COMPARATOR 0 ENABLE */
sbit CP0OUT = CPT0CN ^ 6; /* COMPARATOR 0 OUTPUT */
sbit CP0RIF = CPT0CN ^ 5; /* COMPARATOR 0 RISING EDGE INTERRUPT */
sbit CP0FIF = CPT0CN ^ 4; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
sbit CP0HYP1 = CPT0CN ^ 3; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
sbit CP0HYP0 = CPT0CN ^ 2; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
sbit CP0HYN1 = CPT0CN ^ 1; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
sbit CP0HYN0 = CPT0CN ^ 0; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
/**************************************/
/* CPT1CN 0x88 */
/**************************************/
sbit CP1EN = CPT1CN ^ 7; /* COMPARATOR 1 ENABLE */
sbit CP1OUT = CPT1CN ^ 6; /* COMPARATOR 1 OUTPUT */
sbit CP1RIF = CPT1CN ^ 5; /* COMPARATOR 1 RISING EDGE INTERRUPT */
sbit CP1FIF = CPT1CN ^ 4; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
sbit CP1HYP1 = CPT1CN ^ 3; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
sbit CP1HYP0 = CPT1CN ^ 2; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
sbit CP1HYN1 = CPT1CN ^ 1; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
sbit CP1HYN0 = CPT1CN ^ 0; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
/**************************************/
/* CPT2CN 0x88 */
/**************************************/
sbit CP2EN = CPT2CN ^ 7; /* COMPARATOR 2 ENABLE */
sbit CP2OUT = CPT2CN ^ 6; /* COMPARATOR 2 OUTPUT */
sbit CP2RIF = CPT2CN ^ 5; /* COMPARATOR 2 RISING EDGE INTERRUPT */
sbit CP2FIF = CPT2CN ^ 4; /* COMPARATOR 2 FALLING EDGE INTERRUPT */
sbit CP2HYP1 = CPT2CN ^ 3; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
sbit CP2HYP0 = CPT2CN ^ 2; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
sbit CP2HYN1 = CPT2CN ^ 1; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
sbit CP2HYN0 = CPT2CN ^ 0; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
/**************************************/
/* SCON0 0x98 */
/**************************************/
sbit SM00 = SCON0 ^ 7; /* UART 0 MODE 0 */
sbit SM10 = SCON0 ^ 6; /* UART 0 MODE 1 */
sbit SM20 = SCON0 ^ 5; /* UART 0 MCE */
sbit REN0 = SCON0 ^ 4; /* UART 0 RX ENABLE */
sbit TB80 = SCON0 ^ 3; /* UART 0 TX BIT 8 */
sbit RB80 = SCON0 ^ 2; /* UART 0 RX BIT 8 */
sbit TI0 = SCON0 ^ 1; /* UART 0 TX INTERRUPT FLAG */
sbit RI0 = SCON0 ^ 0; /* UART 0 RX INTERRUPT FLAG */
/**************************************/
/* SCON1 0x98 */
/**************************************/
sbit S0MODE = SCON1 ^ 7; /* UART 1 MODE */
sbit MCE1 = SCON1 ^ 5; /* UART 1 MCE */
sbit REN1 = SCON1 ^ 4; /* UART 1 RX ENABLE */
sbit TB81 = SCON1 ^ 3; /* UART 1 TX BIT 8 */
sbit RB81 = SCON1 ^ 2; /* UART 1 RX BIT 8 */
sbit TI1 = SCON1 ^ 1; /* UART 1 TX INTERRUPT FLAG */
sbit RI1 = SCON1 ^ 0; /* UART 1 RX INTERRUPT FLAG */
/**************************************/
/* IE 0xA8 */
/**************************************/
sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
/**************************************/
/* IP 0xB8 */
/**************************************/
sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
sbit PS = IP ^ 4; /* SERIAL PORT PRIORITY */
sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
/**************************************/
/* SMB0CN 0xC0 */
/**************************************/
sbit BUSY = SMB0CN ^ 7; /* SMBUS 0 BUSY */
sbit ENSMB = SMB0CN ^ 6; /* SMBUS 0 ENABLE */
sbit STA = SMB0CN ^ 5; /* SMBUS 0 START FLAG */
sbit STO = SMB0CN ^ 4; /* SMBUS 0 STOP FLAG */
sbit SI = SMB0CN ^ 3; /* SMBUS 0 INTERRUPT PENDING FLAG */
sbit AA = SMB0CN ^ 2; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
sbit SMBFTE = SMB0CN ^ 1; /* SMBUS 0 FREE TIMER ENABLE */
sbit SMBTOE = SMB0CN ^ 0; /* SMBUS 0 TIMEOUT ENABLE */
/**************************************/
/* CAN0STA 0xC0 */
/**************************************/
sbit BOFF = CAN0STA ^ 7; /* Bus Off Status */
sbit EWARN = CAN0STA ^ 6; /* Warning Status */
sbit EPASS = CAN0STA ^ 5; /* Error Passive */
sbit RXOK = CAN0STA ^ 4; /* Received Message Successfully */
sbit TXOK = CAN0STA ^ 3; /* Transmit a Message Successfully */
sbit LEC2 = CAN0STA ^ 2; /* Last error code bit 2 */
sbit LEC1 = CAN0STA ^ 1; /* Last error code bit 1 */
sbit LEC0 = CAN0STA ^ 0; /* Last error code bit */
/**************************************/
/* TMR2CN 0xC8 */
/**************************************/
sbit TF2 = TMR2CN ^ 7; /* TIMER 2 OVERFLOW FLAG */
sbit EXF2 = TMR2CN ^ 6; /* TIMER 2 EXTERNAL FLAG */
sbit EXEN2 = TMR2CN ^ 3; /* TIMER 2 EXTERNAL ENABLE FLAG */
sbit TR2 = TMR2CN ^ 2; /* TIMER 2 ON/OFF CONTROL */
sbit CT2 = TMR2CN ^ 1; /* TIMER 2 COUNTER SELECT */
sbit CPRL2 = TMR2CN ^ 0; /* TIMER 2 CAPTURE SELECT */
/**************************************/
/* TMR3CN 0xC8 */
/**************************************/
sbit TF3 = TMR3CN ^ 7; /* TIMER 3 OVERFLOW FLAG */
sbit EXF3 = TMR3CN ^ 6; /* TIMER 3 EXTERNAL FLAG */
sbit EXEN3 = TMR3CN ^ 3; /* TIMER 3 EXTERNAL ENABLE FLAG */
sbit TR3 = TMR3CN ^ 2; /* TIMER 3 ON/OFF CONTROL */
sbit CT3 = TMR3CN ^ 1; /* TIMER 3 COUNTER SELECT */
sbit CPRL3 = TMR3CN ^ 0; /* TIMER 3 CAPTURE SELECT */
/**************************************/
/* TMR4CN 0xC8 */
/**************************************/
sbit TF4 = TMR4CN ^ 7; /* TIMER 4 OVERFLOW FLAG */
sbit EXF4 = TMR4CN ^ 6; /* TIMER 4 EXTERNAL FLAG */
sbit EXEN4 = TMR4CN ^ 3; /* TIMER 4 EXTERNAL ENABLE FLAG */
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