nand_flash.h

str710X系列32位ARM外部闪存的接口例子

/******************** (C) COPYRIGHT 2005 STMicroelectronics ********************
* File Name          : nand flash.h
* Author             : EMR - ARM 32 bit Team
* Date First Issued  : 21/Oct/2005
* Description        : This file contains all the functions prototypes for the
*                      NANDxxxW3A NAND FLASH library.
********************************************************************************
* History:
*******************************************************************************/
#include "71x_lib.h"

/*
	Info NAND FLASH - NAND256W3A -> (32MBytes) 256Mbit x8

		256Mbit = 2048 Blocks  
		Block = 32 Pages  [ 16KBytes Main Area + 512 Bytes Spare Area] 	
		Page  = 528 Bytes [	256 (1st Half Pages - Area A) + 
							256 (2st Half Pages - Area B) + 
							16 (Spare Area) ]

		A0-A7 	Column Address 	- 2^8  = 256 (byte for each Pages)
		A8 		Area Address      (0 Area A, 1 Area B)
		A9-A24  Page Address	- 2^16 = 65536 Pages (65536 Half Pages + 65536 Half Pages)
		A9-A13  Address in Block- 2^5  = 32  (Number of Page for each block)
		A14-A24 Address Block  	- 2^11 = 2048(total block numbers)
	
*/

//128mbit x8
#ifdef NAND128RW3A
	#define FLASH_WIDTH           8              /* Flash data width */
    #define FLASH_SIZE            0x1000000      /* Flash size in byte */
    #define PAGE_SIZE             528            /* Page size in word */ 
    #define PAGE_DATA_SIZE        512            /* Page data size in byte */
    #define NUM_BLOCKS		 	  1024           /*number of blocks in device*/
    #define PAGE_SPARE_SIZE       16             /* Spare page size in byte */
 	#define BLOCK_DATA_SIZE		  0x4000		 /* = 16384,  Block Data Size*/
	#define	shift_A8			  1 			 //  Only for Half Page Memory
#endif  

//256mbit x8
#ifdef NAND256RW3A
	#define FLASH_WIDTH           8              /* 32768 Byte or 32M Bytes Flash data width */
	#define FLASH_SIZE            0x2000000      /* Flash size in byte */
	#define PAGE_SIZE             528            /* Page size in word */ 
	#define PAGE_DATA_SIZE        512            /* Page data size in byte */
	#define NUM_BLOCKS		      2048           /* number of blocks in device*/
	#define PAGE_SPARE_SIZE       16             /* Spare page size in byte */
	#define BLOCK_DATA_SIZE		  0x4000		 /* = 16384,  Block Data Size*/
	#define	shift_A8			  1   			 //  Only for Half Page Memory
#endif

#ifdef NAND512RW3A
   #define FLASH_WIDTH           8              /* Flash data width */
   #define FLASH_SIZE            0x4000000      /* Flash size in byte */
   #define PAGE_SIZE             528            /* Page size in byte */ 
   #define PAGE_DATA_SIZE     	 512            /* Page data size in byte */
   #define NUM_BLOCKS		 	 4096           /*number of blocks in device*/
   #define PAGE_SPARE_SIZE       16             /* Spare page size in byte */
   #define shift_A8				 1
   #define BLOCK_DATA_SIZE		 0x4000		    /* = 16384,  Block Data Size*/
#endif 

#ifdef NAND01GRW3A
   #define FLASH_WIDTH           8              /* Flash data width */
   #define FLASH_SIZE            0x8000000      /* Flash size in byte */
   #define PAGE_SIZE             528            /* Page size in byte */ 
   #define PAGE_DATA_SIZE        512            /* Page data size in byte */
   #define NUM_BLOCKS		 	 8192           /*number of blocks in device*/
   #define PAGE_SPARE_SIZE       16             /* Spare page size in byte */
   #define shift_A8		 		 1
   #define BLOCK_DATA_SIZE		 0x4000		    /* = 16384,  Block Data Size*/
#endif 

#define BASEADDR 0x66000000	//	EMI - Bank 3 - CSn.3

#define CLE 0x200000		  // A21	  Command Latch Enable
#define ALE 0x400000		  // A22	  Address Latch Enable

// GPIO <-> Address
#define A20_P24 (0x0001<<4)   // P2.4 - A20
#define A21_P25 (0x0001<<5)   // P2.5 - A21
#define A22_P26 (0x0001<<6)   // P2.6 - A22
#define A23_P27 (0x0001<<7)   // P2.7 - A23
#define CS3_P23 (0x0001<<3)   // P2.3 - CS3
		
//Nand Flash Electronic Signature
#define _NAND128W3A 	 	0x73
#define _NAND256R3A 	 	0x35
#define _NAND256W3A 		0x75
#define _NAND256R4A 	 	0x0045
#define _NAND256W4A 	 	0x0055
#define _NAND512R3A 	 	0x36
#define _NAND512W3A 		0x76
#define _NAND512R4A 	 	0x0046
#define _NAND512W4A 	  	0x0056
#define _NAND01GR3A 	 	0x39
#define _NAND01GW3A 		0x79
#define _NAND01GR4A 	 	0x0049
#define _NAND01GW4A 		0x0059	

//Nand Flash Register Status
#define NandError 			0x01 		//SR0 - Generic Error 	= 1 Error, 0 No Error
#define	NandReady 			0x40		//SR6 - Controller Bit	= 1 Device Ready, 0 Device Busy	
#define NandWriteProtect	0x80		//SR7 - Write Protection= 	1 Not Protect,	0 Protected	


//Nand Flash Commands
#define Nand_AreaA			0x00 
#define Nand_AreaB			0x01 	
#define Nand_AreaC			0x50 	
#define Nand_ReadStatusReg	0x70 	
#define Nand_PageProgram	0x80 
#define Nand_EndPageProg	0x10 	
#define Nand_ReadElectSign	0x90 	
#define Nand_BlockErase		0x60 	
#define Nand_ConfirmErase	0xD0 	
#define Nand_Reset			0xFF 	
#define Nand_CopyBack		0x8A

//Address Mask 
#define MaskAddr_1Cycle		0x000000FF 	//  1癇us Cycle A0  - A7  ( A8 used to select Area )
#define MaskAddr_2Cycle		0x0001FE00 	//  2癇us Cycle	A9	- A16 
#define MaskAddr_3Cycle		0x01FE0000 	//  3癇us Cycle	A17 - A24 
#define MaskAddr_Block		0x01FFC000 	//	A14-A24 Block Address
#define MaskAddr_A09A13		0x00003E00 	//	A9-A13 Address in Block
#define MaskAddr_A09A24		0x07FFFE00 	//	A9-A24 Page Adrress

extern void  NandCommand(u8 cmd);
extern void  NandSendCAddress(u32 address);
extern void  NandSendAddress(u32 address);
extern u8    NandReadStausRegister(void);
extern u16   NandReadEletrocnicSignature(void);
extern void  NandFlashInit (void);
extern void  NandClose(void);
extern void  NandBlockErase(u32 address);
extern void  NandErase_All(void);
extern void  NandCopyPage(u32 address, u32 DestAddr);
extern u8    NandReadData(u32 address);
extern void  NandReadNData(u32 address,u16 N, u8 *Pdata);
extern void  NandWriteByte (u32 address, u8 data);
extern void  NandWriteNBytes(u32 address, u16 N, u8 *vectData);
extern void  Nand_CE_noActive(void);
extern void  Nand_CE_Active(void);