71x_init.s

STR7系列32位ARM控制器的固件库

        LDR		R0,=USBLP_IRQHandler
        LDR		LR,=USBLP_IRQHandler_end
        BX		R0
USBLP_IRQHandler_end:
        SYS_to_IRQ
/********************************************************************************
* Function Name  : T0TOIIRQHandler
* Description    : This function used to switch to SYS mode before entering
                   the T0TOI_IRQHandler function located in 71x_it.c.
                   Then to return to IRQ mode after the
                   T0TOI_IRQHandler function termination.
* Input          : none
* Output         : none
*******************************************************************************/
T0TOIIRQHandler:
        IRQ_to_SYS
        LDR		R0,=T0TOI_IRQHandler
        LDR		LR,=T0TOI_IRQHandler_end
        BX		R0
T0TOI_IRQHandler_end:
        SYS_to_IRQ
/********************************************************************************
* Function Name  : T0OC1IRQHandler
* Description    : This function used to switch to SYS mode before entering
                   the T0OC1_IRQHandler function located in 71x_it.c.
                   Then to return to IRQ mode after the
                   T0OC1_IRQHandler function termination.
* Input          : none
* Output         : none
*******************************************************************************/
T0OC1IRQHandler:
        IRQ_to_SYS
        LDR		R0,=T0OC1_IRQHandler
        LDR		LR,=T0OC1_IRQHandler_end
        BX		R0
T0OC1_IRQHandler_end:
        SYS_to_IRQ
/********************************************************************************
* Function Name  : T0OC2IRQHandler
* Description    : This function used to switch to SYS mode before entering
                   the T0OC2_IRQHandler function located in 71x_it.c.
                   Then to return to IRQ mode after the
                   T0OC2_IRQHandler function termination.
* Input          : none
* Output         : none
*******************************************************************************/
T0OC2IRQHandler:
        IRQ_to_SYS
        LDR		R0,=T0OC2_IRQHandler
        LDR		LR,=T0OC2_IRQHandler_end
        BX		R0
T0OC2_IRQHandler_end:
        SYS_to_IRQ



_start:	
        LDR     pc, =NextInst

NextInst:
 
        NOP   /* Wait for OSC stabilization*/
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
       
           
        MSR    CPSR_c, #Mode_FIQ|I_Bit|F_Bit	/*No interrupts     */
        LDR     SP, =FIQ_Stack           /* Initialize FIQ stack pointer */
        
		  MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit	/*No interrupts     */
        LDR     SP, =IRQ_Stack			/* Initialize IRQ stack pointer*/
		
		  MSR     CPSR_c, #Mode_ABT|F_Bit|I_Bit	/*No interrupts*/
        LDR     SP, =ABT_Stack			/* Initialize ABT stack pointer*/

        MSR     CPSR_c, #Mode_UNDEF|F_Bit|I_Bit	/*No interrupts*/
        LDR     SP, =UNDEF_Stack

        MSR     CPSR_c, #Mode_SVC|F_Bit|I_Bit	/*No interrupts*/
        LDR     SP, =_estack          /*SVC_Stack*/
 /********************************************************************************
* Macro Name     : EMI_INIT
* Description    : Initialize EMI bank 1: 16-bit 15 wait state
* Input          : None.
* Output         : None.
*******************************************************************************/
.if EMI_INIT
        LDR     r0, =GPIO2_Base_addr      /*Configure P2.0 to P2.3 in AF_PP mode*/
        LDR     r2, [r0, #PC0_OFFSET]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC0_OFFSET]
        LDR     r2, [r0, #PC1_OFFSET]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC1_OFFSET]
        LDR     r2, [r0, #PC2_OFFSET]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC2_OFFSET]
        LDR     r0, =EMI_Base_addr
        LDR     r1, =EMI_ENABLE|EMI_SIZE_16
        STR     r1, [r0, #BCON0_OFFSET] /* Enable bank 1 16-bit 15 wait states*/
.endif

/******************************************************************************
*EIC initialization
*Description  : Initialize the EIC as following :
              - IRQ disabled
	   - FIQ disabled
              - IVR contain the load PC opcode (0xF59FF00)
              - Current priority level equal to 0
              - All channels are disabled
              - All channels priority equal to 0
              - All SIR registers contain offset to the related IRQ table entry
******************************************************************************/

 .if EIC_INIT 
        LDR     r3, =EIC_BASE
        LDR     r4, =0x00000000
        STR   	 r4, [r3, #ICR_OFFSET]     /* Disable FIQ AND IRQ */
        STR     r4, [r3, #IER_OFFSET]     /* Disable all channels interrupts */
        LDR     r4, =0xFFFFFFFF
        STR     r4, [r3, #IPR_OFFSET]     /* Clear all IRQ pending bits */
        LDR     r4, =0x0C
        STR     r4, [r3, #FIR_OFFSET]     /* Disable FIQ channels AND clear FIQ pending bits */
        LDR     r4, =0x00000000
        STR     r4, [r3, #CIPR_OFFSET]    /* Reset the current priority register*/
        LDR     r4, =0xE59F0000
        STR     r4, [r3, #IVR_OFFSET]     /* Write the LDR pc,pc,#offset instruction code in IVR[31:16] */
        LDR     r2, =32                   /* 32 Channel to initialize*/
        LDR     R0, =T0TIMI_Addr          /* Read the address of the IRQs address table*/
        LDR     r1, =0x00000FFF
        AND     R0,R0,r1
        LDR     r5, =SIR0_OFFSET          /* Read SIR0 address */
        SUB     r4,R0,#8                  /* subtract 8 for prefetch*/
        LDR     r1, =0xF7E8               /* add the offset to the 0x00000000 address(IVR address + 7E8 = 0x00000000)*/
                                          /* 0xF7E8 used to complete the LDR pc,pc,#offset opcode */
        add     r1,r4,r1                  /* compute the jump offset*/
EIC_INI :
        MOV     r4, r1, LSL #16           /* Left shift the result*/
        STR     r4, [r3, r5]              /* Store the result in SIRx register*/
        ADD     r1, r1, #4                /* Next IRQ address*/
        ADD     r5, r5, #4                /* Next SIR*/
        SUBS    r2, r2, #1                /* Decrement the number of SIR registers to initialize*/
        BNE     EIC_INI                   /* If more then continue*/
 .endif

/*******************************************************************************
* Macro Name     : PERIPHERAL_INIT
* Description    : Disable all device peripherals except EIC.
* Input          : None.
* Output         : None.
*******************************************************************************/
.if PERIPHERAL_INIT
		  LDR     r1, =APB1_BASE          		/*r1= APB1 base address*/
        LDR     r2, =APB2_BASE					/*r2= APB2 base address*/
        LDR     r0, =CKDIS1_config_all
        STRH    r0, [r1, #CKDIS_off_addr]		/*Disable clock for all APB1 peripherals*/
        LDR     r0, =CKDIS2_config_all 
        STRH    r0, [r2, #CKDIS_off_addr]    /*Disable clock for all APB2 peripherals*/
        LDR     r1, =RCCU_PER_Base_addr      /*r1= RCCU_PER base address*/
        LDR     r0, =RCCU_PER_Init           
        STRH    r0, [r1, #RCCU_PER_off_addr] /*To reduce power consumption clear all
                                             unused bits in the RCCU_PER register
                                             and keep EMI and USB KERNEL clocks enabled*/
.endif

/*******************************************************************************
*  			Change to System mode	
******************************************************************************/
		MSR     CPSR_c, #Mode_SYS
      LDR     SP, =USR_Stack           /* Initialize USR/SYS stack pointer*/

/*******************************************************************************
*REMAPPING
*Description  : Remapping  memory whether RAM,FLASH
               at Address 0x0 after the application has started executing.
               Remapping is generally done to allow RAM  to replace FLASH
               at 0x0.
               the remapping of RAM allow copying of vector table into RAM
               To enable the memory remapping uncomment: (see above)
               #define  remapping to enable memory remapping
                  AND
               #define  remap_ram to remap RAM
                  OR
               #define  remap_flash to remap FLASH
******************************************************************************/
.if remapping
    .if remap_flash
        MOV     R0, #FLASH_mask
    .endif
    .if remap_ram
        MOV     R0, #RAM_mask
    .endif

        LDR     r1, =CPM_Base_addr
        LDRH    r2, [r1, #BOOTCR_off_addr]/* Read BOOTCR Register*/
        BIC     r2, r2, #0x03             /* Reset the two LSB bits of BOOTCR*/
        ORR     r2, r2, R0                /* change the two LSB bits of BOOTCR*/
        STRH    r2, [r1, #BOOTCR_off_addr]/* Write BOOTCR Register*/
.endif

	/* copy the initial values for .data section from FLASH to RAM */
		LDR		R1, =_sidata
		LDR		R2, =_sdata
		LDR		R3, =_edata
_reset_inidata_loop:
		CMP		R2, R3
		LDRLO	R0, [R1], #4
		STRLO	R0, [R2], #4
		BLO		_reset_inidata_loop

	/* Clear the .bss section */
		MOV   	R0,#0					   /* get a zero */
		LDR   	r1,=_sbss				/* point to bss start */
		LDR  	r2,=_ebss				   /* point to bss end */
_reset_inibss_loop:
		CMP   	r1,r2					   /* check if some data remains to clear */
		STRLO 	R0,[r1],#4			   /* clear 4 bytes */
		BLO   	_reset_inibss_loop	/* loop until done */
		
/* ---  This is used to define the board oscillator when using RIDE putchar lib ---*/
.if FOSC == 16000000
		MOV	  R0, #0xF40000
		ADD     R0,R0, # 0x2400
		BL		__io_SetMainOscFreq
		
.elseif FOSC == 4000000
		MOV	  R0, #0x3D0000
		ADD     R0,R0, # 0x0900
		BL		__io_SetMainOscFreq
	
.endif

/* --- 		Enter the C code, use B instruction so as to never return 		--- */
     B		main								     


	.end	

/****** (C) COPYRIGHT 2007 STMicroelectronics *********/