71x_init.s

STR7系列32位ARM控制器的固件库

/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name          : 71x_init.s
* Author             : MCD Tools Team
* Version            : V4.0
* Date               : 10/09/2007
* Description        : This is the first code executed after RESET.
*                      This code used to initialize system stacks
*                      and critical peripherals before entering the C code.
*******************************************************************************
 THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
 CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
 AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
 OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
 OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
 CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/

/*;Depending on Your Application, Disable or Enable the following Defines */
 /* ----------------------------------------------------------------------------
  ;                      EMI Bank1 configuration
  ; ----------------------------------------------------------------------------*/
.set EMI_INIT, 0         /* Initialize EMI pins and configure bank1 if 1*/
 /*; ----------------------------------------------------------------------------
  ;                      EIC initialization
  ; ----------------------------------------------------------------------------*/
.set EIC_INIT, 1         /*; Configure and Initialize EIC if 1*/
  /*; ---------------------------------------------------------------------------- 
  ;                      Peripheral  configuration
  ; ---------------------------------------------------------------------------- */   
.set PERIPHERAL_INIT, 1  /* ; Disable all device peripherals except EIC if 1 */   
        
  /*; ---------------------------------------------------------------------------- 
  ;                      Memory remapping
  ; ----------------------------------------------------------------------------*/
.set remapping, 0        /* remap memory before entring the main program if 1 */       
 /* ; ----------------------------------------------------------------------------*/
.set remap_ram, 0        /*; remap SRAM at address 0x00  if 1*/
 /* ; ---------------------------------------------------------------------------*/
.set remap_flash, 0      /* ; remap FLASH at address 0x00 if 1*/


.extern main
.global T0TIMI_Addr

/* ---		the following are useful for initializing the .data section		---*/
.extern _sidata 	/* start address for the initialization values of the .data section. defined in linker script */
.extern _sdata 	/* start address for the .data section. defined in linker script */
.extern _edata 	/* end address for the .data section. defined in linker script */

/* --- 		the following are useful for initializing the .bss section		--- */
.extern _sbss 			/* start address for the .bss section. defined in linker script */
.extern _ebss 			/* end address for the .bss section. defined in linker script */



/* --- 		main oscillator frequency used on the board 	--- */
.equ	FOSC,		16000000 		/*Here set to 16MHz*/


/* --- 		Standard definitions of Mode bits AND Interrupt (I & F) flags in PSRs 		--- */
.set  Mode_USR, 0x10    /* User Mode */
.set  Mode_FIQ, 0x11    /* FIQ Mode */
.set  Mode_IRQ, 0x12    /* IRQ Mode */
.set  Mode_SVC, 0x13    /* Supervisor Mode */
.set  Mode_ABT, 0x17    /* Abort Mode */
.set  Mode_UNDEF, 0x1B  /* Undefined Mode */
.set  Mode_SYS, 0x1F    /* System Mode */

.equ  I_Bit, 0x80       /* when I bit is set, IRQ is disabled */
.equ  F_Bit, 0x40       /* when F bit is set, FIQ is disabled */

/* --- System memory locations */

/* init value for the stack pointer. defined in linker script */
.extern _estack

/* Stack Sizes. The default values are in the linker script, but they can be overriden. */
.extern _UND_Stack_Init
.extern _SVC_Stack_Init
.extern _ABT_Stack_Init
.extern _FIQ_Stack_Init
.extern _IRQ_Stack_Init
.extern _USR_Stack_Init

.extern _UND_Stack_Size
.extern _SVC_Stack_Size
.extern _ABT_Stack_Size
.extern _FIQ_Stack_Size
.extern _IRQ_Stack_Size
.extern _USR_Stack_Size

SVC_Stack           =     _SVC_Stack_Init /*_estack*/           /* 256 byte SVC stack at*/
                                              /* top of memory */
                                              
IRQ_Stack           =     _IRQ_Stack_Init /*SVC_Stack - 256*/     
USR_Stack           =     _USR_Stack_Init /*IRQ_Stack-1024*/    
FIQ_Stack           =     _FIQ_Stack_Init /*USR_Stack-1024*/   
ABT_Stack           =     _ABT_Stack_Init /*FIQ_Stack-256*/     
UNDEF_Stack         =     _UND_Stack_Init /*ABT_Stack-256*/     

.extern EIC_BASE           /* EIC base address */
.equ	ICR_OFFSET,		0x00	/*  Interrupt Control register offset*/
.equ	CICR_OFFSET,	0x04	/* Current Interrupt Channel Register.*/
.equ	CIPR_OFFSET,	0x08	/*  Current Interrupt Priority Register offset*/
.equ	IVR_OFFSET,		0x18	/*  Interrupt Vector Register offset */
.equ	FIR_OFFSET,		0x1C	/*  Fast Interrupt Register offset*/
.equ	IER_OFFSET,		0x20	/* Interrupt Enable Register offset*/
.equ	IPR_OFFSET,		0x40	/* Interrupt Pending Bit Register offset*/
.equ	SIR0_OFFSET,	0x60	/* Source Interrupt Register 0 */

.equ	EMI_Base_addr,	0x6C000000/*  EMI base address*/
.equ	BCON0_OFFSET,	0x00	/* Bank 0 configuration register offset */
.equ	BCON1_OFFSET,	0x04	/*  Bank 1 configuration register offset */
.equ	BCON2_OFFSET,	0x08	/*  Bank 2 configuration register offset */
.equ	BCON3_OFFSET,	0x0C	/*  Bank 3 configuration register offset*/

.equ	EMI_ENABLE,		0x8000
.equ	EMI_SIZE_16,	0x0001

.equ	GPIO2_Base_addr,0xE0005000		/*GPIO2 base address*/
.equ	PC0_OFFSET,		0x00				/* Port Configuration Register 0 offset*/
.equ	PC1_OFFSET,		0x04				/*  Port Configuration Register 1 offset */
.equ	PC2_OFFSET,		0x08				/* Port Configuration Register 2 offset*/
.equ	PD_OFFSET,		0x0C				/* Port Data Register offset*/

.equ	CPM_Base_addr,	0xA0000040		
.equ	BOOTCR_off_addr,0x0010			/* CPM - Boot Configuration Register*/
.equ	FLASH_mask,		0x0000			/* to remap FLASH at 0x0*/
.equ	RAM_mask,		0x0002			/* to remap RAM at 0x0*/

						
.equ  RCCU_PER_Base_addr,0xA0000000	/* RCCU_PER base address*/
.equ	RCCU_PER_Init,		0x14			/* to init RCCU_PER register to reduce power consumption*/
.equ	RCCU_PER_off_addr,	0x1C     /*RCCU_PER register offset*/
/*******************************************************************************
*				APB Bridge  (System Peripheral)
*******************************************************************************/
.extern	APB1_BASE						/*APB Bridge1 Base Address*/
.equ	CKDIS_off_addr,		0x10		/*APB Bridge1 - Clock Disable  Register*/
.equ	CKDIS1_config_all,	0x27FB	/*To disable clock of all APB1s peripherals*/

.extern	APB2_BASE						/*APB Bridge2 Base Address*/
.equ	CKDIS2_config_all,	0x1FDD	/*To disable clock of all APB2s peripherals*/
                                    /* except EIC */
/********************************************************************************
* Macro Name     : SaveContext
* Description    : This macro used to save the context before entering
                   an exception handler.
* Input          : The range of registers to store.
* Output         : none
********************************************************************************/

       .macro SaveContext $R0,$r12
        STMFD  sp!,{R0-r12,LR} /* Save The workspace plus the current return*/
                               /* address LR_ mode into the stack.*/
        MRS    r1,spsr         /* Save the spsr_mode into r1.*/
        STMFD  sp!,{r1}        /* Save spsr.*/
        .endm

/********************************************************************************
* Macro Name     : RestoreContext
* Description    : This macro used to restore the context to return from
                   an exception handler AND continue the program execution.
* Input          : The range of registers to restore.
* Output         : none
********************************************************************************/

        .macro RestoreContext $R0,$r12
        LDMFD   sp!,{r1}        /* Restore the saved spsr_mode into r1.*/
        MSR     spsr_cxsf,r1    /* Restore spsr_mode.*/
        LDMFD   sp!,{R0-r12,pc}^/* Return to the instruction following...*/
                                /* ...the exception interrupt.*/
        .endm
/******************************************************************************
*			Import exception handlers
*******************************************************************************/	
			.extern  Undefined_Handler
			.extern  SWI_Handler
			.extern  Prefetch_Handler
			.extern  Abort_Handler 
			.extern  FIQ_Handler
/******************************************************************************
*			Import IRQ handlers from 71x_it.c
*******************************************************************************/	
			  .extern  T0TIMI_IRQHandler			
	        .extern  FLASH_IRQHandler
	        .extern  RCCU_IRQHandler
	        .extern  RTC_IRQHandler
	        .extern  WDG_IRQHandler
	        .extern  XTI_IRQHandler
	        .extern  USBHP_IRQHandler
	        .extern  I2C0ITERR_IRQHandler
	        .extern  I2C1ITERR_IRQHandler
	        .extern  UART0_IRQHandler
	        .extern  UART1_IRQHandler
	        .extern  UART2_IRQHandler
	        .extern  UART3_IRQHandler
	        .extern  BSPI0_IRQHandler
	        .extern  BSPI1_IRQHandler
	        .extern  I2C0_IRQHandler
	        .extern  I2C1_IRQHandler
	        .extern  CAN_IRQHandler
	        .extern  ADC12_IRQHandler
	        .extern  T1TIMI_IRQHandler
	        .extern  T2TIMI_IRQHandler
	        .extern  T3TIMI_IRQHandler
	        .extern  HDLC_IRQHandler
	        .extern  USBLP_IRQHandler
	        .extern  T0TOI_IRQHandler
	        .extern  T0OC1_IRQHandler
	        .extern  T0OC2_IRQHandler
/******************************************************************************
*		Export Peripherals IRQ handlers table address
*******************************************************************************/


/* --- 			Copy the vector table in the flash 			--- */
			.section .text
			.global _start
			.global _startup
			.arm
_startup:
/* Note: LDR PC instructions are used here, though branch (B) instructions */
/* could also be used, unless the FLASH is at an address >32MB. */
/******************************************************************************
*				Exception vectors
*******************************************************************************/
				Reset_Vec:	LDR		PC, Reset_Addr
				Undef_Vec:	LDR		PC, Undefined_Addr
				SWI_Vec:		LDR		PC, SWI_Addr
				PAbt_Vec:	LDR		PC, Prefetch_Addr
				DAbt_Vec:	LDR		PC, Abort_Addr
								NOP		/* Reserved vector */
				IRQ_Vec:		LDR		PC, IRQ_Addr
				FIQ_Vec:		LDR		PC, FIQ_Addr				

/*******************************************************************************
*				Exception handlers address table
*******************************************************************************/
				Reset_Addr:		.long	_start
				Undefined_Addr:.long	UndefinedHandler
				SWI_Addr:		.long	SWIHandler
				Prefetch_Addr:	.long	PrefetchHandler
				Abort_Addr:		.long	AbortHandler
									.long	0/* reserved */
				IRQ_Addr:		.long	IRQHandler
				FIQ_Addr:		.long	FIQHandler				

/*******************************************************************************
*				Peripherals IRQ handlers address table
*******************************************************************************/
				T0TIMI_Addr:	.long	T0TIMIIRQHandler
				FLASH_Addr:		.long	FLASHIRQHandler
				RCCU_Addr:		.long	RCCUIRQHandler
				RTC_Addr:		.long	RTCIRQHandler
				WDG_Addr:		.long	WDGIRQHandler
				XTI_Addr:		.long	XTIIRQHandler
				USBHP_Addr:		.long	USBHPIRQHandler
				I2C0ITERR_Addr:	.long	I2C0ITERRIRQHandler
				I2C1ITERR_ADDR:	.long	I2C1ITERRIRQHandler
				UART0_Addr:		.long	UART0IRQHandler
				UART1_Addr:		.long	UART1IRQHandler
				UART2_ADDR:		.long	UART2IRQHandler
				UART3_ADDR:		.long	UART3IRQHandler