📄 mpeg4encbf533_icacheonly_cplbtab.c
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/* MANAGED-BY-SYSTEM-BUILDER *//*** CPLB table definitions generated on Apr 28, 2008 at 15:31:14.**** Copyright (C) 2000-2007 Analog Devices Inc., All Rights Reserved.**** This file is generated automatically based upon the options selected** in the LDF Wizard. Changes to the LDF configuration should be made by** changing the appropriate options rather than editing this file.**** Configuration:-** crt_doj: .\Debug\NewProject_basiccrt.doj** processor: ADSP-BF533** si_revision: 0.3** cplb_init_cplb_ctrl: 17** cplb_init_cplb_src_file: G:\vdsp5.0_proj\mpeg4-2.0\encoder\NewProject\NewProject_cplbtab.c** cplb_init_cplb_obj_file: .\Debug\NewProject_cplbtab.doj** using_cplusplus: true** mem_init: false** use_vdk: false** use_eh: true** use_argv: false** running_from_internal_memory: true** user_heap_src_file: G:\vdsp5.0_proj\mpeg4-2.0\encoder\NewProject\NewProject_heaptab.c** libraries_use_stdlib: true** libraries_use_fileio_libs: false** libraries_use_ieeefp_emulation_libs: false** libraries_use_eh_enabled_libs: false** system_heap: L3** system_heap_size: 16K** system_stack: SCRATCHPAD** system_stack_min_size: 3K** use_sdram: true** use_sdram_size: 64M** use_sdram_partitioned: custom***/#ifdef _MISRA_RULES#pragma diag(push)#pragma diag(suppress:misra_rule_2_2)#pragma diag(suppress:misra_rule_8_10)#pragma diag(suppress:misra_rule_10_1_a)#endif /* _MISRA_RULES */#define CACHE_MEM_MODE CPLB_DNOCACHE#include <sys/platform.h>#include <cplbtab.h>#pragma section("cplb_data")cplb_entry dcplbs_table[] = {/*$VDSG<customisable-data-cplb-table> *//* This code is preserved if the CPLB tables are re-generated. */ // end of section - termination {0xffffffff, 0}, /*$VDSG<customisable-data-cplb-table> */}; /* dcplbs_table */cplb_entry icplbs_table[] = {/*$VDSG<customisable-instr-cplb-table> *//* This code is preserved if the CPLB tables are re-generated. */ {0xFFA00000, (PAGE_SIZE_1MB | CPLB_LOCK | CPLB_VALID) }, // L1A Code {0x01A00000, (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)}, // SDRAM Cache Code {0x01B00000, (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID)}, // SDRAM NoCache Code // end of section - termination {0xffffffff, 0}, /*$VDSG<customisable-instr-cplb-table> */}; /* icplbs_table */#ifdef _MISRA_RULES#pragma diag(pop)#endif /* _MISRA_RULES */
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